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Message-ID: <CAPDyKFoBJBunAU_cBocmNGSN5DwDYaLVd_BR6MYwysQKAwUkxw@mail.gmail.com>
Date: Mon, 25 Mar 2019 14:27:00 +0100
From: Ulf Hansson <ulf.hansson@...aro.org>
To: Sowjanya Komatineni <skomatineni@...dia.com>
Cc: Adrian Hunter <adrian.hunter@...el.com>,
Rob Herring <robh+dt@...nel.org>,
Mark Rutland <mark.rutland@....com>,
Harjani Ritesh <riteshh@...eaurora.org>,
Thierry Reding <thierry.reding@...il.com>,
Jon Hunter <jonathanh@...dia.com>, anrao@...dia.com,
linux-tegra <linux-tegra@...r.kernel.org>,
Linux Kernel Mailing List <linux-kernel@...r.kernel.org>,
"linux-mmc@...r.kernel.org" <linux-mmc@...r.kernel.org>,
DTML <devicetree@...r.kernel.org>
Subject: Re: [PATCH V4 01/10] mmc: tegra: fix ddr signaling for non-ddr modes
On Sun, 24 Mar 2019 at 05:45, Sowjanya Komatineni
<skomatineni@...dia.com> wrote:
>
> ddr_signaling is set to true for DDR50 and DDR52 modes but is
> not set back to false for other modes. This programs incorrect
> host clock when mode change happens from DDR52/DDR50 to other
> SDR or HS modes like incase of mmc_retune where it switches
> from HS400 to HS DDR and then from HS DDR to HS mode and then
> to HS200.
>
> This patch fixes the ddr_signaling to set properly for non DDR
> modes.
>
> Tested-by: Jon Hunter <jonathanh@...dia.com>
> Acked-by: Adrian Hunter <adrian.hunter@...el.com>
> Signed-off-by: Sowjanya Komatineni <skomatineni@...dia.com>
Applied the series for next, except patch 5 and 10 as those are from arm-soc.
In regards to $subject patch I added a stable tag.
Kind regards
Uffe
> ---
> drivers/mmc/host/sdhci-tegra.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/drivers/mmc/host/sdhci-tegra.c b/drivers/mmc/host/sdhci-tegra.c
> index 32e62904c0d3..46086dd43bfb 100644
> --- a/drivers/mmc/host/sdhci-tegra.c
> +++ b/drivers/mmc/host/sdhci-tegra.c
> @@ -779,6 +779,7 @@ static void tegra_sdhci_set_uhs_signaling(struct sdhci_host *host,
> bool set_dqs_trim = false;
> bool do_hs400_dll_cal = false;
>
> + tegra_host->ddr_signaling = false;
> switch (timing) {
> case MMC_TIMING_UHS_SDR50:
> case MMC_TIMING_UHS_SDR104:
> --
> 2.7.4
>
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