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Date:   Tue, 26 Mar 2019 01:11:41 +0100 (CET)
From:   Thomas Gleixner <tglx@...utronix.de>
To:     Kan Liang <kan.liang@...ux.intel.com>
cc:     peterz@...radead.org, acme@...nel.org, mingo@...hat.com,
        linux-kernel@...r.kernel.org, jolsa@...nel.org, eranian@...gle.com,
        alexander.shishkin@...ux.intel.com, ak@...ux.intel.com
Subject: Re: [PATCH V3 01/23] perf/x86: Support outputting XMM registers

On Fri, 22 Mar 2019, kan.liang@...ux.intel.com wrote:
> 
> +	PERF_REG_X86_XMM15 = 62,
> +
> +	/* All registers include the XMMX registers */
> +	PERF_REG_X86_MAX = PERF_REG_X86_XMM15 + 2,

Ergo: PERF_REG_X86_MAX == 64

> -#define REG_RESERVED (~((1ULL << PERF_REG_X86_MAX) - 1ULL))
> +#define REG_RESERVED \
> +	(PERF_REG_X86_MAX == 64 ? 0 : ~((1ULL << PERF_REG_X86_MAX)) - 1ULL)

So what the heck is this conditional for?

But now 32bit has also access to the upper 8 GPRs simply because
REG_RESERVED is now 0 and REG_NOSUPPORT is not excluding them either.

Thanks,

	tglx

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