linux-kernel - RE: [PATCH v2] RISC-V: Implement ASID allocator

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Date:   Tue, 9 Apr 2019 03:36:03 +0000
From:   Anup Patel <Anup.Patel@....com>
To:     Guo Ren <guoren@...nel.org>
CC:     Palmer Dabbelt <palmer@...ive.com>,
        Albert Ou <aou@...s.berkeley.edu>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        Mike Rapoport <rppt@...ux.ibm.com>,
        Christoph Hellwig <hch@...radead.org>,
        Atish Patra <Atish.Patra@....com>, Gary Guo <gary@...yguo.net>,
        Paul Walmsley <paul.walmsley@...ive.com>,
        "linux-riscv@...ts.infradead.org" <linux-riscv@...ts.infradead.org>
Subject: RE: [PATCH v2] RISC-V: Implement ASID allocator



> -----Original Message-----
> From: Guo Ren <guoren@...nel.org>
> Sent: Tuesday, April 9, 2019 8:33 AM
> To: Anup Patel <Anup.Patel@....com>
> Cc: Palmer Dabbelt <palmer@...ive.com>; Albert Ou
> <aou@...s.berkeley.edu>; linux-kernel@...r.kernel.org; Mike Rapoport
> <rppt@...ux.ibm.com>; Christoph Hellwig <hch@...radead.org>; Atish Patra
> <Atish.Patra@....com>; Gary Guo <gary@...yguo.net>; Paul Walmsley
> <paul.walmsley@...ive.com>; linux-riscv@...ts.infradead.org
> Subject: Re: [PATCH v2] RISC-V: Implement ASID allocator
> 
> Hi Anup,
> 
> On Thu, Mar 28, 2019 at 06:32:36AM +0000, Anup Patel wrote:
> > This patch is tested on QEMU/virt machine and SiFive Unleashed board.
> > On QEMU/virt machine, we see 10% (approx) performance improvement
> with
> > SW emulated TLBs provided by QEMU. Unfortunately, ASID bits of SATP
> > CSR are not implemented on SiFive Unleashed board so we don't see any
> > change in performance.
> Can you tell me what is the test case ?

I am testing this using hackbench.

Regards,
Anup