linux-kernel - Re: [PATCH] ARM: dts: rockchip: Remove unnecessary setting of UART0 SCLK rate on veyron

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Date:   Wed, 10 Apr 2019 16:53:28 -0700
From:   Doug Anderson <dianders@...omium.org>
To:     Matthias Kaehlcke <mka@...omium.org>
Cc:     Heiko Stuebner <heiko@...ech.de>, Rob Herring <robh+dt@...nel.org>,
        Mark Rutland <mark.rutland@....com>,
        Linux ARM <linux-arm-kernel@...ts.infradead.org>,
        "open list:ARM/Rockchip SoC..." <linux-rockchip@...ts.infradead.org>,
        devicetree@...r.kernel.org, LKML <linux-kernel@...r.kernel.org>,
        Douglas Anderson <dianders@...omium.org>
Subject: Re: [PATCH] ARM: dts: rockchip: Remove unnecessary setting of UART0
 SCLK rate on veyron

Hi,

On Wed, Apr 10, 2019 at 11:30 AM Matthias Kaehlcke <mka@...omium.org> wrote:
>
> Some veyron devices have a Bluetooth controller connected on UART0.
> The UART needs to operate at a high speed, however setting the clock
> rate at initialization has no practical effect. During initialization
> user space adjusts the UART baudrate multiple times, which ends up
> changing the SCLK rate. After a successful initiatalization the clk
> is running at the desired speed (48MHz).
>
> Remove the unnecessary clock rate configuration from the DT.
>
> Signed-off-by: Matthias Kaehlcke <mka@...omium.org>
> ---
>  arch/arm/boot/dts/rk3288-veyron.dtsi | 4 ----
>  1 file changed, 4 deletions(-)

Nice.  Looks like this hasn't been needed for a while.  Back in 3.14
when I first added this it was important because "8250_dw.c" didn't
have a clk_set_rate() in it, but seems like it's been there forever
now.

Reviewed-by: Douglas Anderson <dianders@...omium.org>