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Date:   Thu, 11 Apr 2019 13:36:41 +0200
From:   Heiko Stuebner <>
To:     Matthias Kaehlcke <>
Cc:     Rob Herring <>,
        Mark Rutland <>,,,,,
        Douglas Anderson <>
Subject: Re: [PATCH] ARM: dts: rockchip: Remove unnecessary setting of UART0 SCLK rate on veyron

Am Mittwoch, 10. April 2019, 20:30:10 CEST schrieb Matthias Kaehlcke:
> Some veyron devices have a Bluetooth controller connected on UART0.
> The UART needs to operate at a high speed, however setting the clock
> rate at initialization has no practical effect. During initialization
> user space adjusts the UART baudrate multiple times, which ends up
> changing the SCLK rate. After a successful initiatalization the clk
> is running at the desired speed (48MHz).
> Remove the unnecessary clock rate configuration from the DT.
> Signed-off-by: Matthias Kaehlcke <>

applied for 5.2 with Doug's RB.


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