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Message-ID: <155501368210.20095.61816680073374889@swboyd.mtv.corp.google.com>
Date: Thu, 11 Apr 2019 13:14:42 -0700
From: Stephen Boyd <sboyd@...nel.org>
To: Nicolas Boichat <drinkcat@...omium.org>,
Weiyi Lu <weiyi.lu@...iatek.com>
Cc: Matthias Brugger <matthias.bgg@...il.com>,
Stephen Boyd <sboyd@...eaurora.org>,
Rob Herring <robh@...nel.org>,
James Liao <jamesjj.liao@...iatek.com>,
Fan Chen <fan.chen@...iatek.com>,
linux-arm Mailing List <linux-arm-kernel@...ts.infradead.org>,
lkml <linux-kernel@...r.kernel.org>,
"moderated list:ARM/Mediatek SoC support"
<linux-mediatek@...ts.infradead.org>, linux-clk@...r.kernel.org,
srv_heupstream <srv_heupstream@...iatek.com>,
stable@...r.kernel.org, Owen Chen <owen.chen@...iatek.com>
Subject: Re: [PATCH v5 3/9] clk: mediatek: Add configurable pcwibits and fmin to mtk_pll_data
Quoting Nicolas Boichat (2019-03-07 22:20:27)
> On Tue, Mar 5, 2019 at 1:06 PM Weiyi Lu <weiyi.lu@...iatek.com> wrote:
> >
> > From: Owen Chen <owen.chen@...iatek.com>
> >
> > 1. pcwibits: The integer bits of pcw for plls is extend to 8 bits,
> > add a variable to indicate this change and
> > backward-compatible.
> > 2. fmin: The pll freqency lower-bound is vary from 1GMhz to
>
> Minor nit: frequency (Stephen I guess you could fix that when applying...)
What's a 1GMhz? Anyway, fixed the typo.
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