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Date:   Thu, 11 Apr 2019 13:16:16 -0700
From:   Stephen Boyd <sboyd@...nel.org>
To:     Matthias Brugger <matthias.bgg@...il.com>,
        Nicolas Boichat <drinkcat@...omium.org>,
        Rob Herring <robh@...nel.org>,
        Stephen Boyd <sboyd@...eaurora.org>,
        Weiyi Lu <weiyi.lu@...iatek.com>
Cc:     James Liao <jamesjj.liao@...iatek.com>,
        Fan Chen <fan.chen@...iatek.com>,
        linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org,
        linux-mediatek@...ts.infradead.org, linux-clk@...r.kernel.org,
        srv_heupstream@...iatek.com, stable@...r.kernel.org,
        Weiyi Lu <weiyi.lu@...iatek.com>,
        Owen Chen <owen.chen@...iatek.com>
Subject: Re: [PATCH v5 1/9] clk: mediatek: Disable tuner_en before change PLL rate

Quoting Weiyi Lu (2019-03-04 21:05:38)
> From: Owen Chen <owen.chen@...iatek.com>
> 
> PLLs with tuner_en bit, such as APLL1, need to disable
> tuner_en before apply new frequency settings, or the new frequency
> settings (pcw) will not be applied.
> The tuner_en bit will be disabled during changing PLL rate
> and be restored after new settings applied.
> 
> Fixes: e2f744a82d725 (clk: mediatek: Add MT2712 clock support)
> Cc: <stable@...r.kernel.org>
> Signed-off-by: Owen Chen <owen.chen@...iatek.com>
> Signed-off-by: Weiyi Lu <weiyi.lu@...iatek.com>
> ---

Applied to clk-next

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