linux-kernel - Re: [PATCH v5 3/9] clk: mediatek: Add configurable pcwibits and fmin to mtk_pll

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Message-ID: <155501378408.20095.2407243439182851286@swboyd.mtv.corp.google.com>
Date:   Thu, 11 Apr 2019 13:16:24 -0700
From:   Stephen Boyd <sboyd@...nel.org>
To:     Matthias Brugger <matthias.bgg@...il.com>,
        Nicolas Boichat <drinkcat@...omium.org>,
        Rob Herring <robh@...nel.org>,
        Stephen Boyd <sboyd@...eaurora.org>,
        Weiyi Lu <weiyi.lu@...iatek.com>
Cc:     James Liao <jamesjj.liao@...iatek.com>,
        Fan Chen <fan.chen@...iatek.com>,
        linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org,
        linux-mediatek@...ts.infradead.org, linux-clk@...r.kernel.org,
        srv_heupstream@...iatek.com, stable@...r.kernel.org,
        Weiyi Lu <weiyi.lu@...iatek.com>,
        Owen Chen <owen.chen@...iatek.com>
Subject: Re: [PATCH v5 3/9] clk: mediatek: Add configurable pcwibits and fmin to mtk_pll_data

Quoting Weiyi Lu (2019-03-04 21:05:40)
> From: Owen Chen <owen.chen@...iatek.com>
> 
> 1. pcwibits: The integer bits of pcw for plls is extend to 8 bits,
>    add a variable to indicate this change and
>    backward-compatible.
> 2. fmin: The pll freqency lower-bound is vary from 1GMhz to
>    1.5Ghz, add a variable to indicate platform-dependent.
> 
> Signed-off-by: Owen Chen <owen.chen@...iatek.com>
> Signed-off-by: Weiyi Lu <weiyi.lu@...iatek.com>
> Acked-by: Sean Wang <sean.wang@...nel.org>
> ---

Applied to clk-next