linux-kernel - RE: [PATCH 1/2] stmmac: introduce flag to dynamically disable TX offload for rockchip devices

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Date:   Fri, 12 Apr 2019 07:35:05 +0000
From:   Jose Abreu <jose.abreu@...opsys.com>
To:     "Leonidas P. Papadakos" <papadakospan@...il.com>,
        Robin Murphy <robin.murphy@....com>
CC:     Jose Abreu <jose.abreu@...opsys.com>,
        Philipp Tomsich <philipp.tomsich@...obroma-systems.com>,
        Heiko Stübner <heiko@...ech.de>,
        Christoph Müllner 
        <christoph.muellner@...obroma-systems.com>,
        Maxime Coquelin <mcoquelin.stm32@...il.com>,
        Alexandre Torgue <alexandre.torgue@...com>,
        "netdev@...r.kernel.org" <netdev@...r.kernel.org>,
        LKML <linux-kernel@...r.kernel.org>,
        Linux ARM <linux-arm-kernel@...ts.infradead.org>,
        Klaus Goger <klaus.goger@...obroma-systems.com>
Subject: RE: [PATCH 1/2] stmmac: introduce flag to dynamically disable TX
 offload for rockchip devices

From: Leonidas P. Papadakos <papadakospan@...il.com>
Date: Thu, Apr 11, 2019 at 22:09:30

> 
> At this point I've settled on snps,txpbl = <0x20> by itself.
> If I increase the MTU from the default of 1500 I get a stack trace and 
> link reset almost immediately:
> (https://urldefense.proofpoint.com/v2/url?u=https-3A__pastebin.com_raw_5JBtfWei&d=DwIBAg&c=DPL6_X_6JkXFx7AXWqB0tg&r=WHDsc6kcWAl4i96Vm5hJ_19IJiuxx_p_Rzo2g-uHDKw&m=4VBEjla4XZR8-m8v84wV5TnhbHyIvTniApjuk2XMoS8&s=piZ9ECO216D0lthteXLpCiOvlHwJhq-x_pBKChT274Y&e=)
> whether TX Checksumming is ON or OFF.

Can you please share the stacktrace here ? I can't access pastebin due to 
corporate policy.

If it's a queue timeout then please share your "dmesg | grep -i stmmac" 
since boot.

> 
> That said, with the default MTU, I get better speeds when TX 
> Checksumming is on and the PBL tweak is set.
> 
> Is there a better option in the horizon for the near future?
> At least for the Renegade (the only board I have to test) it can serve 
> as a temporary workaround.
> Should I make a patch to replace force_thresh_dma_mode with txbpl 
> <0x20> for the Renegade specifically?
> 
> In any case I would be happy to help as much as I can to figure out if 
> it's a board specific thing, or SoC, or even an issue of the Ethernet 
> device itself.

This is not a workaround neither an issue. It's well stablished that PBL 
setting interferes with COE so one must choose a setting that depends on 
FIFO size. I would like to make it automatic in the driver but I didn't 
have the time to submit a patch yet, sorry.

Thanks,
Jose Miguel Abreu