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Date:   Fri, 12 Apr 2019 13:45:59 +0200
From:   Heiko Stübner <heiko@...ech.de>
To:     Elaine Zhang <zhangqing@...k-chips.com>
Cc:     mturquette@...libre.com, sboyd@...nel.org,
        linux-clk@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
        linux-rockchip@...ts.infradead.org, linux-kernel@...r.kernel.org,
        xxx@...k-chips.com, xf@...k-chips.com, huangtao@...k-chips.com
Subject: Re: [PATCH v1 4/6] clk: rockchip: add a clock-type for muxes based in the pmugrf

Hi Elaine,

Am Mittwoch, 3. April 2019, 11:42:27 CEST schrieb Elaine Zhang:
> Rockchip socs often have some tiny number of muxes not controlled from
> the core clock controller but through bits set in the pmugrf.
> Use MUXPMUGRF() to cover this special clock-type.
> 
> Signed-off-by: Elaine Zhang <zhangqing@...k-chips.com>

Do you have an example for such a clock?

I.e. on rk3399 we have the pmucru which already links
to the pmugrf as its "regular" rockchip,grf.
Similarly the main-cru links to the main grf.

So I don't really see where a clock needs to be defined
in the main-grf and use a bit from the pmugrf.

Similarly I wasn't really able to find anything that looks like
a clock-mux in the PX30's (rk3326) pmugrf.

So I'd really like an example beforehand :-D

Thanks
Heiko

> ---
>  drivers/clk/rockchip/clk.c |  9 +++++++++
>  drivers/clk/rockchip/clk.h | 17 +++++++++++++++++
>  2 files changed, 26 insertions(+)
> 
> diff --git a/drivers/clk/rockchip/clk.c b/drivers/clk/rockchip/clk.c
> index 0a8a694a41ab..875412043dd7 100644
> --- a/drivers/clk/rockchip/clk.c
> +++ b/drivers/clk/rockchip/clk.c
> @@ -415,6 +415,8 @@ struct rockchip_clk_provider * __init rockchip_clk_init(struct device_node *np,
>  
>  	ctx->grf = syscon_regmap_lookup_by_phandle(ctx->cru_node,
>  						   "rockchip,grf");
> +	ctx->pmugrf = syscon_regmap_lookup_by_phandle(ctx->cru_node,
> +						   "rockchip,pmugrf");
>  
>  	return ctx;
>  
> @@ -490,6 +492,13 @@ void __init rockchip_clk_register_branches(
>  				list->mux_shift, list->mux_width,
>  				list->mux_flags);
>  			break;
> +		case branch_muxpmugrf:
> +			clk = rockchip_clk_register_muxgrf(list->name,
> +				list->parent_names, list->num_parents,
> +				flags, ctx->pmugrf, list->muxdiv_offset,
> +				list->mux_shift, list->mux_width,
> +				list->mux_flags);
> +			break;
>  		case branch_divider:
>  			if (list->div_table)
>  				clk = clk_register_divider_table(NULL,
> diff --git a/drivers/clk/rockchip/clk.h b/drivers/clk/rockchip/clk.h
> index 20200a707611..1b30346f11e1 100644
> --- a/drivers/clk/rockchip/clk.h
> +++ b/drivers/clk/rockchip/clk.h
> @@ -234,6 +234,7 @@ struct rockchip_clk_provider {
>  	struct clk_onecell_data clk_data;
>  	struct device_node *cru_node;
>  	struct regmap *grf;
> +	struct regmap *pmugrf;
>  	spinlock_t lock;
>  };
>  
> @@ -386,6 +387,7 @@ enum rockchip_clk_branch_type {
>  	branch_composite,
>  	branch_mux,
>  	branch_muxgrf,
> +	branch_muxpmugrf,
>  	branch_divider,
>  	branch_fraction_divider,
>  	branch_gate,
> @@ -658,6 +660,21 @@ struct rockchip_clk_branch {
>  		.gate_offset	= -1,				\
>  	}
>  
> +#define MUXPMUGRF(_id, cname, pnames, f, o, s, w, mf)		\
> +	{							\
> +		.id		= _id,				\
> +		.branch_type	= branch_muxpmugrf,		\
> +		.name		= cname,			\
> +		.parent_names	= pnames,			\
> +		.num_parents	= ARRAY_SIZE(pnames),		\
> +		.flags		= f,				\
> +		.muxdiv_offset	= o,				\
> +		.mux_shift	= s,				\
> +		.mux_width	= w,				\
> +		.mux_flags	= mf,				\
> +		.gate_offset	= -1,				\
> +	}
> +
>  #define DIV(_id, cname, pname, f, o, s, w, df)			\
>  	{							\
>  		.id		= _id,				\
> 




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