linux-kernel - Re: [PATCH v1 1/6] clk: rockchip: Add supprot to limit input rate for fractional divider

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Message-ID: <818a6e0a-d99b-7350-9c4a-9e0a0d12122a@theobroma-systems.com>
Date:   Fri, 12 Apr 2019 14:12:52 +0200
From:   Christoph Müllner 
        <christoph.muellner@...obroma-systems.com>
To:     Heiko Stübner <heiko@...ech.de>,
        Elaine Zhang <zhangqing@...k-chips.com>
Cc:     mturquette@...libre.com, sboyd@...nel.org,
        linux-clk@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
        linux-rockchip@...ts.infradead.org, linux-kernel@...r.kernel.org,
        xxx@...k-chips.com, xf@...k-chips.com, huangtao@...k-chips.com,
        Finley Xiao <finley.xiao@...k-chips.com>
Subject: Re: [PATCH v1 1/6] clk: rockchip: Add supprot to limit input rate for
 fractional divider

Hi Heiko,

On 12.04.19 13:52, Heiko Stübner wrote:
> Hi Elaine,
> 
> Am Mittwoch, 3. April 2019, 11:42:24 CEST schrieb Elaine Zhang:
>> From: Finley Xiao <finley.xiao@...k-chips.com>
>>
>> From Rockchips fractional divider usage, some clocks can be generated
>> by fractional divider, but the input clock frequency of fractional
>> divider should be less than a specified value.
>>
>> Signed-off-by: Finley Xiao <finley.xiao@...k-chips.com>
>> Signed-off-by: Elaine Zhang <zhangqing@...k-chips.com>
> 
> can you tell me where these maximum input values come from?
> 
> I talked to Christoph from Theobroma (Cc'ed) last week and he mentioned
> that they're using the fractional divider with a higher input frequency
> to create a very specific frequency [some details are gone from my memory
> though] they can't get otherwise.
> 
> So I really don't want to break their working setup by introducing barriers
> that are not strictly necessary.
> 
> @Christoph: can you describe the bits from your fractional setup that
> I've forgotten please?

We need to set the I2S0 clock to 24.56 MHz.

When restricting the input frequency to a maximum of 600 Mhz,
we could use the integer divider to get 400 Mhz (dividing by 2).
However, with the 400 Mhz as input to the frac divider,
we run into the problem, that the maximum possible output frequency
is 20 MHz (there is another restriction which states that the
fraction input : output frequency must be >= 20).

Thanks,
Christoph

> 
>> diff --git a/drivers/clk/rockchip/clk-px30.c b/drivers/clk/rockchip/clk-px30.c
>> index 601a77f1af78..ccabce35580b 100644
>> --- a/drivers/clk/rockchip/clk-px30.c
>> +++ b/drivers/clk/rockchip/clk-px30.c
>> @@ -21,6 +21,7 @@
>>  #include "clk.h"
>>  
>>  #define PX30_GRF_SOC_STATUS0		0x480
>> +#define PX30_FRAC_MAX_PRATE		600000000
> 
> 
>> diff --git a/drivers/clk/rockchip/clk-rk3368.c b/drivers/clk/rockchip/clk-rk3368.c
>> index 7c4d242f19c1..67c2da5e7d61 100644
>> --- a/drivers/clk/rockchip/clk-rk3368.c
>> +++ b/drivers/clk/rockchip/clk-rk3368.c
>> @@ -20,6 +20,9 @@
>>  #include "clk.h"
>>  
>>  #define RK3368_GRF_SOC_STATUS0	0x480
>> +#define RK3368_I2S_FRAC_MAX_PRATE       600000000
>> +#define RK3368_UART_FRAC_MAX_PRATE	600000000
>> +#define RK3368_SPDIF_FRAC_MAX_PRATE	600000000
> 
>> diff --git a/drivers/clk/rockchip/clk-rk3399.c b/drivers/clk/rockchip/clk-rk3399.c
>> index 5a628148f3f0..1d81382bd3e0 100644
>> --- a/drivers/clk/rockchip/clk-rk3399.c
>> +++ b/drivers/clk/rockchip/clk-rk3399.c
>> @@ -21,6 +21,12 @@
>>  #include <dt-bindings/clock/rk3399-cru.h>
>>  #include "clk.h"
>>  
>> +#define RK3399_I2S_FRAC_MAX_PRATE       600000000
>> +#define RK3399_UART_FRAC_MAX_PRATE	600000000
>> +#define RK3399_SPDIF_FRAC_MAX_PRATE	600000000
>> +#define RK3399_VOP_FRAC_MAX_PRATE	600000000
>> +#define RK3399_WIFI_FRAC_MAX_PRATE	600000000
>> +
> 
> 
>