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Message-ID: <tip-f08c47d1f86c6dc666c7e659d94bf6d4492aa9d7@git.kernel.org>
Date:   Tue, 16 Apr 2019 04:39:00 -0700
From:   tip-bot for Kan Liang <tipbot@...or.com>
To:     linux-tip-commits@...r.kernel.org
Cc:     torvalds@...ux-foundation.org, tglx@...utronix.de,
        vincent.weaver@...ne.edu, linux-kernel@...r.kernel.org,
        hpa@...or.com, mingo@...nel.org, acme@...hat.com,
        kan.liang@...ux.intel.com, jolsa@...hat.com,
        alexander.shishkin@...ux.intel.com, peterz@...radead.org,
        eranian@...gle.com
Subject: [tip:perf/core] perf/x86/intel/cstate: Add Icelake support

Commit-ID:  f08c47d1f86c6dc666c7e659d94bf6d4492aa9d7
Gitweb:     https://git.kernel.org/tip/f08c47d1f86c6dc666c7e659d94bf6d4492aa9d7
Author:     Kan Liang <kan.liang@...ux.intel.com>
AuthorDate: Tue, 2 Apr 2019 12:45:06 -0700
Committer:  Ingo Molnar <mingo@...nel.org>
CommitDate: Tue, 16 Apr 2019 12:26:18 +0200

perf/x86/intel/cstate: Add Icelake support

Icelake uses the same C-state residency events as Sandy Bridge.

Signed-off-by: Kan Liang <kan.liang@...ux.intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@...radead.org>
Cc: Alexander Shishkin <alexander.shishkin@...ux.intel.com>
Cc: Arnaldo Carvalho de Melo <acme@...hat.com>
Cc: Jiri Olsa <jolsa@...hat.com>
Cc: Linus Torvalds <torvalds@...ux-foundation.org>
Cc: Peter Zijlstra <peterz@...radead.org>
Cc: Stephane Eranian <eranian@...gle.com>
Cc: Thomas Gleixner <tglx@...utronix.de>
Cc: Vince Weaver <vincent.weaver@...ne.edu>
Cc: acme@...nel.org
Cc: jolsa@...nel.org
Link: https://lkml.kernel.org/r/20190402194509.2832-10-kan.liang@linux.intel.com
Signed-off-by: Ingo Molnar <mingo@...nel.org>
---
 arch/x86/events/intel/cstate.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/x86/events/intel/cstate.c b/arch/x86/events/intel/cstate.c
index 94a4b7fc75d0..dd5658ec31d5 100644
--- a/arch/x86/events/intel/cstate.c
+++ b/arch/x86/events/intel/cstate.c
@@ -578,6 +578,8 @@ static const struct x86_cpu_id intel_cstates_match[] __initconst = {
 	X86_CSTATES_MODEL(INTEL_FAM6_ATOM_GOLDMONT_X, glm_cstates),
 
 	X86_CSTATES_MODEL(INTEL_FAM6_ATOM_GOLDMONT_PLUS, glm_cstates),
+
+	X86_CSTATES_MODEL(INTEL_FAM6_ICELAKE_MOBILE, snb_cstates),
 	{ },
 };
 MODULE_DEVICE_TABLE(x86cpu, intel_cstates_match);

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