linux-kernel - Re: [PATCH RESEND] clk: tegra: Don't enable already enabled PLLs

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Message-ID: <155571237296.15276.7432257601401549388@swboyd.mtv.corp.google.com>
Date:   Fri, 19 Apr 2019 15:19:32 -0700
From:   Stephen Boyd <sboyd@...nel.org>
To:     Dmitry Osipenko <digetx@...il.com>,
        Jonathan Hunter <jonathanh@...dia.com>,
        Michael Turquette <mturquette@...libre.com>,
        Peter De Schrijver <pdeschrijver@...dia.com>,
        Prashant Gaikwad <pgaikwad@...dia.com>,
        Thierry Reding <thierry.reding@...il.com>
Cc:     linux-clk@...r.kernel.org, linux-tegra@...r.kernel.org,
        linux-kernel@...r.kernel.org
Subject: Re: [PATCH RESEND] clk: tegra: Don't enable already enabled PLLs

Quoting Dmitry Osipenko (2019-04-19 04:42:26)
> Initially Common Clock Framework isn't aware of the clock-enable status,
> this results in enabling of clocks that were enabled by bootloader. This
> is not a big deal for a regular clock-gates, but for PLL's it may have
> some unpleasant consequences. Thus re-enabling PLLX (the main CPU parent
> clock) may result in extra long period of PLL re-locking.
> 
> Acked-by: Peter De Schrijver <pdeschrijver@...dia.com>
> Signed-off-by: Dmitry Osipenko <digetx@...il.com>
> ---

Applied to clk-next