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Message-ID: <CA+M3ks5M1NXWj1dew9DcNfOhYeFbWZ6iVYDcvQr6auVAKUnVyA@mail.gmail.com>
Date: Wed, 24 Apr 2019 14:25:41 +0200
From: Benjamin Gaignard <benjamin.gaignard@...aro.org>
To: Philippe CORNU <philippe.cornu@...com>
Cc: Yannick FERTRE <yannick.fertre@...com>,
Vincent ABRIOU <vincent.abriou@...com>,
David Airlie <airlied@...ux.ie>,
Daniel Vetter <daniel@...ll.ch>,
Maxime Coquelin <mcoquelin.stm32@...il.com>,
Alexandre TORGUE <alexandre.torgue@...com>,
"dri-devel@...ts.freedesktop.org" <dri-devel@...ts.freedesktop.org>,
"linux-stm32@...md-mailman.stormreply.com"
<linux-stm32@...md-mailman.stormreply.com>,
"linux-arm-kernel@...ts.infradead.org"
<linux-arm-kernel@...ts.infradead.org>,
"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH] drm/stm: ltdc: update planes at next vblank to avoid
partial refresh
Le lun. 1 avr. 2019 à 11:22, Philippe CORNU <philippe.cornu@...com> a écrit :
>
> Dear Yannick,
> Thank you for your patch, works fine,
>
> Acked-by: Philippe Cornu <philippe.cornu@...com>
>
Applied on drm-misc-next,
Thanks,
Benjamin
> Philippe :-)
>
> On 4/1/19 9:24 AM, Yannick Fertré wrote:
> > Plane updates must be synchronized on vblank with the shadow register mechanism
> > to avoid partial refresh on screen.
> >
> > Signed-off-by: Yannick Fertré <yannick.fertre@...com>
> > ---
> > drivers/gpu/drm/stm/ltdc.c | 4 ++--
> > 1 file changed, 2 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/stm/ltdc.c b/drivers/gpu/drm/stm/ltdc.c
> > index b1741a9..c2d0800 100644
> > --- a/drivers/gpu/drm/stm/ltdc.c
> > +++ b/drivers/gpu/drm/stm/ltdc.c
> > @@ -426,8 +426,8 @@ static void ltdc_crtc_atomic_enable(struct drm_crtc *crtc,
> > /* Enable IRQ */
> > reg_set(ldev->regs, LTDC_IER, IER_RRIE | IER_FUIE | IER_TERRIE);
> >
> > - /* Immediately commit the planes */
> > - reg_set(ldev->regs, LTDC_SRCR, SRCR_IMR);
> > + /* Commit shadow registers = update planes at next vblank */
> > + reg_set(ldev->regs, LTDC_SRCR, SRCR_VBR);
> >
> > /* Enable LTDC */
> > reg_set(ldev->regs, LTDC_GCR, GCR_LTDCEN);
> >
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