linux-kernel - Re: [PATCH] clk: ingenic/jz4725b: Fix parent of pixel clock

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [day] [month] [year] [list]

Message-ID: <155657875909.168659.9064792203031956186@swboyd.mtv.corp.google.com>
Date:   Mon, 29 Apr 2019 15:59:19 -0700
From:   Stephen Boyd <sboyd@...nel.org>
To:     Paul Cercueil <paul@...pouillou.net>
Cc:     Michael Turquette <mturquette@...libre.com>,
        linux-clk@...r.kernel.org, linux-kernel@...r.kernel.org,
        stable@...r.kernel.org
Subject: Re: [PATCH] clk: ingenic/jz4725b: Fix parent of pixel clock

Quoting Paul Cercueil (2019-04-29 13:53:11)
> Hi Stephen,
> 
> Le jeu. 18 avril 2019 à 23:58, Stephen Boyd <sboyd@...nel.org> a 
> écrit :
> > Quoting Paul Cercueil (2019-04-17 04:24:20)
> >>  The pixel clock is directly connected to the output of the PLL, and 
> >> not
> >>  to the /2 divider.
> >> 
> >>  Cc: stable@...r.kernel.org
> >>  Fixes: 226dfa4726eb ("clk: Add Ingenic jz4725b CGU driver")
> >>  Signed-off-by: Paul Cercueil <paul@...pouillou.net>
> >>  ---
> > 
> > Applied to clk-next
> 
> Could you drop this patch?
> 
> It turns out it is wrong and the pixel clock is really connected to the 
> "pll half"
> clock. The real bug was elsewhere: the "pll half" clock does not report 
> the correct
> rate. I will send a patch for this one later.
> 

Ok. No problem.