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Date:   Wed, 1 May 2019 18:47:10 +0000
From:   Rasmus Villemoes <>
To:     Joakim Tjernlund <>,
        "" <>,
        "" <>,
        "" <>
CC:     "" <>,
        "" <>,
        "" <>,
        "" <>,
        Rasmus Villemoes <>,
        "" <>,
Subject: Re: [PATCH v2 4/6] dt-bindings: soc/fsl: qe: document new
 fsl,qe-snums binding

On 01/05/2019 17.12, Joakim Tjernlund wrote:
> On Wed, 2019-05-01 at 09:29 +0000, Rasmus Villemoes wrote:
>> CAUTION: This email originated from outside of the organization. Do not click links or open attachments unless you recognize the sender and know the content is safe.
>> Reading table 4-30, and its footnotes, of the QUICC Engine Block
>> Reference Manual shows that the set of snum _values_ is not
>> necessarily just a function of the _number_ of snums, as given in the
>> fsl,qe-num-snums property.
>> As an alternative, to make it easier to add support for other variants
>> of the QUICC engine IP, this introduces a new binding fsl,qe-snums,
>> which automatically encodes both the number of snums and the actual
>> values to use.
>> For example, for the MPC8309, one would specify the property as
>>                fsl,qe-snums = /bits/ 8 <
>>                        0x88 0x89 0x98 0x99 0xa8 0xa9 0xb8 0xb9
>>                        0xc8 0xc9 0xd8 0xd9 0xe8 0xe9>;
> I think you need add this example to the qe.txt doc itselft.

Sure, can do.

> BTW, what is /bits/ ?

That indicates that the numbers should be stored as an array of u8, and
not as by default an array of (big-endian) 32-bit numbers. See

This is already used in some bindings and existing .dts (e.g.
hwmon/aspeed-pwm-tacho.txt, but git grep shows many more).


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