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Message-ID: <20190501202149.GM8007@atomide.com>
Date: Wed, 1 May 2019 13:21:49 -0700
From: Tony Lindgren <tony@...mide.com>
To: Sebastian Andrzej Siewior <bigeasy@...utronix.de>
Cc: "kernelci.org bot" <bot@...nelci.org>, Tejun Heo <tj@...nel.org>,
Peter Zijlstra <peterz@...radead.org>,
tomeu.vizoso@...labora.com, guillaume.tucker@...labora.com,
mgalka@...labora.com, Thomas Gleixner <tglx@...utronix.de>,
broonie@...nel.org, matthew.hart@...aro.org, khilman@...libre.com,
enric.balletbo@...labora.com, Ingo Molnar <mingo@...nel.org>,
Lai Jiangshan <jiangshanlai@...il.com>,
Johannes Weiner <hannes@...xchg.org>,
linux-kernel@...r.kernel.org, Ingo Molnar <mingo@...hat.com>,
Kevin Hilman <khilman@...nel.org>, linux-omap@...r.kernel.org
Subject: Re: next/master boot bisection: next-20190430 on beagle-xm
Hi,
* Sebastian Andrzej Siewior <bigeasy@...utronix.de> [190501 19:03]:
> On 2019-05-01 10:44:31 [-0700], Tony Lindgren wrote:
> > Hmm so I tried without "earlycon" in command line thinking it might be
> > happening with just "earlyprintk" but still no luck.
> >
> > BTW, in general you might want to update your kernel command line
> > options to:
> >
> > debug earlyprintk earlycon
>
> debug. Let me look if I manage to hide that `debug' from systemd…
Oh that.. I've been quite happy with openrc now for years :)
> > Looking at the oops 0xfa1cc000, so 0x481cc000 I guess which is d_can0?
>
> That node around it I guess.
OK I found two issues. It seems that d_can also needs osc clock
on am335x. And there's no revision register for d_can.. We're now
reading the CTL register unnecessarily.
Below is what I hope fixes the boot issue for you, care to boot
test?
If this helps I'll send out proper patches for for both issues.
Regards,
Tony
8< ----------------------
diff --git a/arch/arm/boot/dts/am33xx-l4.dtsi b/arch/arm/boot/dts/am33xx-l4.dtsi
--- a/arch/arm/boot/dts/am33xx-l4.dtsi
+++ b/arch/arm/boot/dts/am33xx-l4.dtsi
@@ -1762,8 +1762,9 @@
reg = <0xcc000 0x4>;
reg-names = "rev";
/* Domains (P, C): per_pwrdm, l4ls_clkdm */
- clocks = <&l4ls_clkctrl AM3_L4LS_D_CAN0_CLKCTRL 0>;
- clock-names = "fck";
+ clocks = <&l4ls_clkctrl AM3_L4LS_D_CAN0_CLKCTRL 0>,
+ <&dcan0_fck>;
+ clock-names = "fck", "osc";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0xcc000 0x2000>;
@@ -1785,8 +1786,9 @@
reg = <0xd0000 0x4>;
reg-names = "rev";
/* Domains (P, C): per_pwrdm, l4ls_clkdm */
- clocks = <&l4ls_clkctrl AM3_L4LS_D_CAN1_CLKCTRL 0>;
- clock-names = "fck";
+ clocks = <&l4ls_clkctrl AM3_L4LS_D_CAN1_CLKCTRL 0>,
+ <&dcan1_fck>;
+ clock-names = "fck", "osc";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0xd0000 0x2000>;
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