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Message-Id: <20190503091507.6159-1-simon.k.r.goldschmidt@gmail.com>
Date:   Fri,  3 May 2019 11:15:07 +0200
From:   Simon Goldschmidt <simon.k.r.goldschmidt@...il.com>
To:     Dinh Nguyen <dinguyen@...nel.org>
Cc:     Marek Vasut <marek.vasut@...il.com>,
        Dalon Westergreen <dalon.westergreen@...ux.intel.com>,
        Simon Goldschmidt <simon.k.r.goldschmidt@...il.com>,
        linux-arm-kernel@...ts.infradead.org,
        Russell King <linux@...linux.org.uk>,
        linux-kernel@...r.kernel.org
Subject: [PATCH] arm: socfpga: execute cold reboot by default

This changes system reboot for socfpga to issue a cold reboot by
default instead of a warm reboot.

Warm reboot can still be used by setting reboot_mode to
REBOOT_WARM (e.g. via kernel command line 'reboot='), but this
patch ensures cold reboot is issued for both REBOOT_COLD and
REBOOT_HARD.

Also, cold reboot is more fail safe than warm reboot has some
issues at least fo CSEL=0 and BSEL=qspi, where the boot rom does
not set the qspi clock to a valid range.

Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@...il.com>
---

See discussion in this thread on the u-boot ML:
https://lists.denx.de/pipermail/u-boot/2019-April/367463.html
---
 arch/arm/mach-socfpga/socfpga.c | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/arch/arm/mach-socfpga/socfpga.c b/arch/arm/mach-socfpga/socfpga.c
index 816da0eb6..6abfbf140 100644
--- a/arch/arm/mach-socfpga/socfpga.c
+++ b/arch/arm/mach-socfpga/socfpga.c
@@ -85,10 +85,10 @@ static void socfpga_cyclone5_restart(enum reboot_mode mode, const char *cmd)
 
 	temp = readl(rst_manager_base_addr + SOCFPGA_RSTMGR_CTRL);
 
-	if (mode == REBOOT_HARD)
-		temp |= RSTMGR_CTRL_SWCOLDRSTREQ;
-	else
+	if (mode == REBOOT_WARM)
 		temp |= RSTMGR_CTRL_SWWARMRSTREQ;
+	else
+		temp |= RSTMGR_CTRL_SWCOLDRSTREQ;
 	writel(temp, rst_manager_base_addr + SOCFPGA_RSTMGR_CTRL);
 }
 
@@ -98,10 +98,10 @@ static void socfpga_arria10_restart(enum reboot_mode mode, const char *cmd)
 
 	temp = readl(rst_manager_base_addr + SOCFPGA_A10_RSTMGR_CTRL);
 
-	if (mode == REBOOT_HARD)
-		temp |= RSTMGR_CTRL_SWCOLDRSTREQ;
-	else
+	if (mode == REBOOT_WARM)
 		temp |= RSTMGR_CTRL_SWWARMRSTREQ;
+	else
+		temp |= RSTMGR_CTRL_SWCOLDRSTREQ;
 	writel(temp, rst_manager_base_addr + SOCFPGA_A10_RSTMGR_CTRL);
 }
 
-- 
2.20.1

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