lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <a8a3c429-307c-40fc-12b4-d62374bfda1d@gmail.com>
Date:   Fri, 10 May 2019 12:49:55 -0700
From:   Florian Fainelli <f.fainelli@...il.com>
To:     John Garry <john.garry@...wei.com>, linux-kernel@...r.kernel.org,
        Will Deacon <will.deacon@....com>,
        Mark Rutland <mark.rutland@....com>
Cc:     Peter Zijlstra <peterz@...radead.org>,
        Ingo Molnar <mingo@...hat.com>,
        Arnaldo Carvalho de Melo <acme@...nel.org>,
        Alexander Shishkin <alexander.shishkin@...ux.intel.com>,
        Jiri Olsa <jolsa@...hat.com>,
        Namhyung Kim <namhyung@...nel.org>,
        Catalin Marinas <catalin.marinas@....com>,
        "moderated list:ARM PMU PROFILING AND DEBUGGING" 
        <linux-arm-kernel@...ts.infradead.org>
Subject: Re: [PATCH v2] perf vendor events arm64: Add Cortex-A57 and
 Cortex-A72 events

On 5/6/19 12:25 AM, John Garry wrote:
> On 03/05/2019 00:47, Florian Fainelli wrote:
>> The Cortex-A57 and Cortex-A72 both support all ARMv8 recommended events
>> up to the RC_ST_SPEC (0x91) event with the exception of:
>>
>> - L1D_CACHE_REFILL_INNER (0x44)
>> - L1D_CACHE_REFILL_OUTER (0x45)
>> - L1D_TLB_RD (0x4E)
>> - L1D_TLB_WR (0x4F)
>> - L2D_TLB_REFILL_RD (0x5C)
>> - L2D_TLB_REFILL_WR (0x5D)
>> - L2D_TLB_RD (0x5E)
>> - L2D_TLB_WR (0x5F)
>> - STREX_SPEC (0x6F)
>>
>> Create an appropriate JSON file for mapping those events and update the
>> mapfile.csv for matching the Cortex-A57 and Cortex-A72 MIDR to that
>> file.
> 
> I suppose you could have also created separate a72 and a57 folders, and
> used a symbolic link for the json. That would have kept the folder
> structure consistent and neat.

Will, Mark, any preference on that? Either way works fine.

> 
>>
>> Signed-off-by: Florian Fainelli <f.fainelli@...il.com>
> Apart from the above:
> 
> Reviewed-by: John Garry <john.garry@...wei.com>

Thanks

> 
>> ---
>> Changes in v2:
>>
>> - added a shared directory for both Cortex-A57 and A72 (Will)
>> - removed unsupported ARMv8 v3 events (John)
>>
>>  .../arm/cortex-a57-a72/core-imp-def.json      | 179 ++++++++++++++++++
>>  tools/perf/pmu-events/arch/arm64/mapfile.csv  |   2 +
>>  2 files changed, 181 insertions(+)
>>  create mode 100644
>> tools/perf/pmu-events/arch/arm64/arm/cortex-a57-a72/core-imp-def.json
>>
>> diff --git a/tools/perf/pmu-even
> 


-- 
Florian

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ