linux-kernel - Re: [PATCH v2] perf vendor events arm64: Add Cortex-A57 and Cortex-A72 events

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Message-ID: <20190513111427.GC6711@fuggles.cambridge.arm.com>
Date:   Mon, 13 May 2019 12:14:27 +0100
From:   Will Deacon <will.deacon@....com>
To:     Florian Fainelli <f.fainelli@...il.com>
Cc:     John Garry <john.garry@...wei.com>, linux-kernel@...r.kernel.org,
        Mark Rutland <mark.rutland@....com>,
        Peter Zijlstra <peterz@...radead.org>,
        Ingo Molnar <mingo@...hat.com>,
        Arnaldo Carvalho de Melo <acme@...nel.org>,
        Alexander Shishkin <alexander.shishkin@...ux.intel.com>,
        Jiri Olsa <jolsa@...hat.com>,
        Namhyung Kim <namhyung@...nel.org>,
        Catalin Marinas <catalin.marinas@....com>,
        "moderated list:ARM PMU PROFILING AND DEBUGGING" 
        <linux-arm-kernel@...ts.infradead.org>
Subject: Re: [PATCH v2] perf vendor events arm64: Add Cortex-A57 and
 Cortex-A72 events

On Fri, May 10, 2019 at 12:49:55PM -0700, Florian Fainelli wrote:
> On 5/6/19 12:25 AM, John Garry wrote:
> > On 03/05/2019 00:47, Florian Fainelli wrote:
> >> The Cortex-A57 and Cortex-A72 both support all ARMv8 recommended events
> >> up to the RC_ST_SPEC (0x91) event with the exception of:
> >>
> >> - L1D_CACHE_REFILL_INNER (0x44)
> >> - L1D_CACHE_REFILL_OUTER (0x45)
> >> - L1D_TLB_RD (0x4E)
> >> - L1D_TLB_WR (0x4F)
> >> - L2D_TLB_REFILL_RD (0x5C)
> >> - L2D_TLB_REFILL_WR (0x5D)
> >> - L2D_TLB_RD (0x5E)
> >> - L2D_TLB_WR (0x5F)
> >> - STREX_SPEC (0x6F)
> >>
> >> Create an appropriate JSON file for mapping those events and update the
> >> mapfile.csv for matching the Cortex-A57 and Cortex-A72 MIDR to that
> >> file.
> > 
> > I suppose you could have also created separate a72 and a57 folders, and
> > used a symbolic link for the json. That would have kept the folder
> > structure consistent and neat.
> 
> Will, Mark, any preference on that? Either way works fine.

I'd personally avoid committing symbolic links if possible, so I'm fine
with your patch as-is.

Will