linux-kernel - Re: [PATCH v12 2/3] spi: Add Renesas R-Car Gen3 RPC-IF SPI controller driver

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Date:   Wed, 15 May 2019 13:55:05 +0800
From:   masonccyang@...c.com.tw
To:     "Lee Jones" <lee.jones@...aro.org>
Cc:     bbrezillon@...nel.org, broonie@...nel.org,
        devicetree@...r.kernel.org,
        "Geert Uytterhoeven" <geert+renesas@...der.be>,
        "Simon Horman" <horms@...ge.net.au>, juliensu@...c.com.tw,
        linux-kernel@...r.kernel.org, linux-renesas-soc@...r.kernel.org,
        linux-spi@...r.kernel.org, marek.vasut@...il.com,
        mark.rutland@....com, robh+dt@...nel.org,
        sergei.shtylyov@...entembedded.com, zhengxunli@...c.com.tw
Subject: Re: [PATCH v12 2/3] spi: Add Renesas R-Car Gen3 RPC-IF SPI controller
 driver

Hi Jones,

> > +
> > +struct rpc_spi {
> > +   struct rpc_mfd *mfd;
> 
> The term MFD isn't a real thing.  What you're obtaining below is
> driver data and is normally articulated as 'ddata' in drivers.

yes, it's just imply that data is from MFD.

Should I rename "mfd" ?

> 
> > +   u32 cur_speed_hz;
> > +   u32 cmd;
> > +   u32 addr;
> > +   u32 dummy;
> > +   u32 smcr;
> > +   u32 smenr;
> > +   u32 xferlen;
> > +   u32 totalxferlen;
> > +   enum spi_mem_data_dir xfer_dir;
> > +};
> 
> [...]
> 
> > +static void rpc_spi_hw_init(struct rpc_spi *rpc)
> > +{
> > +   //
> > +   // NOTE: The 0x260 are undocumented bits, but they must be set.
> > +   //    RPC_PHYCNT_STRTIM is strobe timing adjustment bit,
> > +   //    0x0 : the delay is biggest,
> > +   //    0x1 : the delay is 2nd biggest,
> > +   //    On H3 ES1.x, the value should be 0, while on others,
> > +   //    the value should be 6.
> > +   //
> 
> C++ style comments?  Is that a thing now?

It's kind of Mark's previous comments.

> 
> > +   regmap_write(rpc->mfd->regmap, RPC_PHYCNT, RPC_PHYCNT_CAL |
> > +              RPC_PHYCNT_STRTIM(6) | 0x260);
> > +
> > +   //
> > +   // NOTE: The 0x1511144 are undocumented bits, but they must be set
> > +   //       for RPC_PHYOFFSET1.
> > +   //    The 0x31 are undocumented bits, but they must be set
> > +   //    for RPC_PHYOFFSET2.
> > +   //
> > +   regmap_write(rpc->mfd->regmap, RPC_PHYOFFSET1,
> > +           RPC_PHYOFFSET1_DDRTMG(3) | 0x1511144);
> > +   regmap_write(rpc->mfd->regmap, RPC_PHYOFFSET2, 0x31 |
> > +           RPC_PHYOFFSET2_OCTTMG(4));
> > +   regmap_write(rpc->mfd->regmap, RPC_SSLDR, RPC_SSLDR_SPNDL(7) |
> > +           RPC_SSLDR_SLNDL(7) | RPC_SSLDR_SCKDL(7));
> > +   regmap_write(rpc->mfd->regmap, RPC_CMNCR, RPC_CMNCR_MD |
> > +           RPC_CMNCR_SFDE | RPC_CMNCR_MOIIO_HIZ | RPC_CMNCR_IOFV_HIZ 
|
> > +           RPC_CMNCR_BSZ(0));
> > +}
> 
> -- 
> Lee Jones [李琼斯]
> Linaro Services Technical Lead
> Linaro.org │ Open source software for ARM SoCs
> Follow Linaro: Facebook | Twitter | Blog

thanks & best regards,
Mason

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