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Message-ID: <20190517172648.GA18164@agluck-desk>
Date: Fri, 17 May 2019 10:26:49 -0700
From: "Luck, Tony" <tony.luck@...el.com>
To: Borislav Petkov <bp@...en8.de>
Cc: "Ghannam, Yazen" <Yazen.Ghannam@....com>,
"linux-edac@...r.kernel.org" <linux-edac@...r.kernel.org>,
"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
"x86@...nel.org" <x86@...nel.org>
Subject: Re: [PATCH v3 5/6] x86/MCE: Save MCA control bits that get set in
hardware
On Fri, May 17, 2019 at 06:37:29PM +0200, Borislav Petkov wrote:
> Now, the
>
> wrmsrl(msr_ops.ctl(i), -1)
> rdmsrl(msr_ops.ctl(i), val);
>
> method of throwing all 1s to see what sticks is what Intel wants, as
> Tony said. Is that going to be a problem on AMD?
It is what we want in general ... but there is this:
if (c->x86_vendor == X86_VENDOR_INTEL) {
/*
* SDM documents that on family 6 bank 0 should not be written
* because it aliases to another special BIOS controlled
* register.
* But it's not aliased anymore on model 0x1a+
* Don't ignore bank 0 completely because there could be a
* valid event later, merely don't write CTL0.
*/
if (c->x86 == 6 && c->x86_model < 0x1A && cfg->banks > 0)
mce_banks[0].init = 0;
Which is a quirk for some models where we don't want to do
the "write all 1s and see what sticks"
-Tony
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