linux-kernel - Re: [PATCH 2/3] arm64: dts: freescale: Add i.MX8MN dtsi support

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Message-ID: <CAOMZO5D1B1tKs8eu_a8hXs193+TukHAYHiCEyk5g63p1S-cnbg@mail.gmail.com>
Date:   Fri, 31 May 2019 08:39:49 -0300
From:   Fabio Estevam <festevam@...il.com>
To:     Yongcai Huang <Anson.Huang@....com>
Cc:     Rob Herring <robh+dt@...nel.org>,
        Mark Rutland <mark.rutland@....com>,
        Shawn Guo <shawnguo@...nel.org>,
        Sascha Hauer <s.hauer@...gutronix.de>,
        Sascha Hauer <kernel@...gutronix.de>,
        Andrey Smirnov <andrew.smirnov@...il.com>,
        Manivannan Sadhasivam <manivannan.sadhasivam@...aro.org>,
        Bruno Thomsen <bruno.thomsen@...il.com>,
        Dong Aisheng <aisheng.dong@....com>,
        Ping Bai <ping.bai@....com>, Li Yang <leoyang.li@....com>,
        Lucas Stach <l.stach@...gutronix.de>, pankaj.bansal@....com,
        Bhaskar Upadhaya <bhaskar.upadhaya@....com>,
        Pramod Kumar <pramod.kumar_1@....com>,
        Vabhav Sharma <vabhav.sharma@....com>,
        Leonard Crestez <leonard.crestez@....com>,
        "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" 
        <devicetree@...r.kernel.org>,
        linux-kernel <linux-kernel@...r.kernel.org>,
        "moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE" 
        <linux-arm-kernel@...ts.infradead.org>,
        NXP Linux Team <Linux-imx@....com>
Subject: Re: [PATCH 2/3] arm64: dts: freescale: Add i.MX8MN dtsi support

On Thu, May 30, 2019 at 6:45 AM <Anson.Huang@....com> wrote:

> +                       gpio1: gpio@...00000 {
> +                               compatible = "fsl,imx8mn-gpio", "fsl,imx35-gpio";
> +                               reg = <0x30200000 0x10000>;
> +                               interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
> +                                            <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;

No GPIO clocks entries?

> +                       usbphynop1: usbphynop1 {
> +                               compatible = "usb-nop-xceiv";
> +                               clocks = <&clk IMX8MN_CLK_USB_PHY_REF>;
> +                               assigned-clocks = <&clk IMX8MN_CLK_USB_PHY_REF>;
> +                               assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_100M>;
> +                               clock-names = "main_clk";
> +                       };

 usbphynop1 does not have any registers associated, so it should be
placed outside the soc.

Building with W=1 should warn you about that.

> +                       usbphynop2: usbphynop2 {
> +                               compatible = "usb-nop-xceiv";
> +                               clocks = <&clk IMX8MN_CLK_USB_PHY_REF>;
> +                               assigned-clocks = <&clk IMX8MN_CLK_USB_PHY_REF>;
> +                               assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_100M>;
> +                               clock-names = "main_clk";
> +                       };
> +

Ditto