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Date: Fri, 31 May 2019 08:54:02 +0530 From: Manivannan Sadhasivam <manivannan.sadhasivam@...aro.org> To: Jianqun Xu <jay.xu@...k-chips.com> Cc: heiko@...ech.de, mark.rutland@....com, robh+dt@...nel.org, zhangzj@...k-chips.com, linux-rockchip@...ts.infradead.org, linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org, devicetree@...r.kernel.org Subject: Re: [PATCH v3 1/1] arm64: dts: rockchip: add core dtsi file for RK3399Pro SoCs On Thu, May 30, 2019 at 08:08:48AM +0800, Jianqun Xu wrote: > This patch adds core dtsi file for Rockchip RK3399Pro SoCs, > include rk3399.dtsi. Also enable pciei0/pcie_phy for AP to > talk to NPU part inside SoC. > > Signed-off-by: Jianqun Xu <jay.xu@...k-chips.com> > --- > changes since v2: > - only enable pcie0 and pcie_phy nodes, thanks for Heiko and manivannan > > changes since v1: > - remove dfi and dmc > > arch/arm64/boot/dts/rockchip/rk3399pro.dtsi | 22 +++++++++++++++++++++ > 1 file changed, 22 insertions(+) > create mode 100644 arch/arm64/boot/dts/rockchip/rk3399pro.dtsi > > diff --git a/arch/arm64/boot/dts/rockchip/rk3399pro.dtsi b/arch/arm64/boot/dts/rockchip/rk3399pro.dtsi > new file mode 100644 > index 000000000000..bb5ebf6608b9 > --- /dev/null > +++ b/arch/arm64/boot/dts/rockchip/rk3399pro.dtsi > @@ -0,0 +1,22 @@ > +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) > +// Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd. > + > +#include "rk3399.dtsi" > + > +/ { > + compatible = "rockchip,rk3399pro"; > +}; > + > +/* Default to enabled since AP talk to NPU part over pcie */ > +&pcie_phy { > + status = "okay"; > +}; > + > +/* Default to enabled since AP talk to NPU part over pcie */ > +&pcie0 { > + ep-gpios = <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>; > + num-lanes = <4>; > + pinctrl-names = "default"; > + pinctrl-0 = <&pcie_clkreqn_cpm>; No pinctrl config for ep-gpio? Other than that, it looks good to me. Acked-by: Manivannan Sadhasivam <manivannan.sadhasivam@...aro.org> Thanks, Mani > + status = "okay"; > +}; > -- > 2.17.1 > > >
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