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Message-ID: <e11c1e55-1e11-7ce3-3c0f-0b723ab260aa@prevas.se>
Date:   Mon, 3 Jun 2019 19:53:36 +0000
From:   Rasmus Villemoes <Rasmus.Villemoes@...vas.se>
To:     "devicetree@...r.kernel.org" <devicetree@...r.kernel.org>,
        Qiang Zhao <qiang.zhao@....com>, Li Yang <leoyang.li@....com>
CC:     "linuxppc-dev@...ts.ozlabs.org" <linuxppc-dev@...ts.ozlabs.org>,
        "linux-arm-kernel@...ts.infradead.org" 
        <linux-arm-kernel@...ts.infradead.org>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        Rob Herring <robh+dt@...nel.org>,
        Scott Wood <oss@...error.net>,
        Christophe Leroy <christophe.leroy@....fr>,
        Mark Rutland <mark.rutland@....com>,
        Joakim Tjernlund <Joakim.Tjernlund@...inera.com>
Subject: Re: [PATCH v3 0/6] soc/fsl/qe: cleanups and new DT binding

On 13/05/2019 13.14, Rasmus Villemoes wrote:
> This small series consists of some small cleanups and simplifications
> of the QUICC engine driver, and introduces a new DT binding that makes
> it much easier to support other variants of the QUICC engine IP block
> that appears in the wild: There's no reason to expect in general that
> the number of valid SNUMs uniquely determines the set of such, so it's
> better to simply let the device tree specify the values (and,
> implicitly via the array length, also the count).
> 
> Which tree should this go through?

Ping? These patches should be ready to go in, but I don't know who is
supposed to pick them up.

Thanks,
Rasmus

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