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Message-ID: <tip-1f157286829c78c0bd8e495951a5c098d88e3d1a@git.kernel.org>
Date: Mon, 3 Jun 2019 06:28:59 -0700
From: tip-bot for Jiri Olsa <tipbot@...or.com>
To: linux-tip-commits@...r.kernel.org
Cc: acme@...nel.org, peterz@...radead.org,
torvalds@...ux-foundation.org, linux-kernel@...r.kernel.org,
alexander.shishkin@...ux.intel.com, jolsa@...nel.org,
namhyung@...nel.org, gregkh@...uxfoundation.org, hpa@...or.com,
tglx@...utronix.de, mingo@...nel.org
Subject: [tip:perf/core] perf/x86: Use update attribute groups for caps
Commit-ID: 1f157286829c78c0bd8e495951a5c098d88e3d1a
Gitweb: https://git.kernel.org/tip/1f157286829c78c0bd8e495951a5c098d88e3d1a
Author: Jiri Olsa <jolsa@...nel.org>
AuthorDate: Sun, 12 May 2019 17:55:15 +0200
Committer: Ingo Molnar <mingo@...nel.org>
CommitDate: Mon, 3 Jun 2019 11:58:24 +0200
perf/x86: Use update attribute groups for caps
Using the new pmu::update_attrs attribute group for
"caps" directory.
Signed-off-by: Jiri Olsa <jolsa@...nel.org>
Signed-off-by: Peter Zijlstra (Intel) <peterz@...radead.org>
Cc: Alexander Shishkin <alexander.shishkin@...ux.intel.com>
Cc: Arnaldo Carvalho de Melo <acme@...nel.org>
Cc: Greg Kroah-Hartman <gregkh@...uxfoundation.org>
Cc: Linus Torvalds <torvalds@...ux-foundation.org>
Cc: Namhyung Kim <namhyung@...nel.org>
Cc: Peter Zijlstra <peterz@...radead.org>
Cc: Thomas Gleixner <tglx@...utronix.de>
Link: https://lkml.kernel.org/r/20190512155518.21468-7-jolsa@kernel.org
Signed-off-by: Ingo Molnar <mingo@...nel.org>
---
arch/x86/events/core.c | 8 --------
arch/x86/events/intel/core.c | 25 ++++++++++++++++++++-----
arch/x86/events/perf_event.h | 1 -
3 files changed, 20 insertions(+), 14 deletions(-)
diff --git a/arch/x86/events/core.c b/arch/x86/events/core.c
index b831091d4c10..dd0996ba75c3 100644
--- a/arch/x86/events/core.c
+++ b/arch/x86/events/core.c
@@ -1821,14 +1821,6 @@ static int __init init_hw_perf_events(void)
x86_pmu_format_group.attrs = x86_pmu.format_attrs;
- if (x86_pmu.caps_attrs) {
- struct attribute **tmp;
-
- tmp = merge_attr(x86_pmu_caps_group.attrs, x86_pmu.caps_attrs);
- if (!WARN_ON(!tmp))
- x86_pmu_caps_group.attrs = tmp;
- }
-
if (!x86_pmu.events_sysfs_show)
x86_pmu_events_group.attrs = &empty_attrs;
diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c
index 600e87055ba9..d4002e71a0b8 100644
--- a/arch/x86/events/intel/core.c
+++ b/arch/x86/events/intel/core.c
@@ -4411,6 +4411,12 @@ pebs_is_visible(struct kobject *kobj, struct attribute *attr, int i)
return x86_pmu.pebs ? attr->mode : 0;
}
+static umode_t
+lbr_is_visible(struct kobject *kobj, struct attribute *attr, int i)
+{
+ return x86_pmu.lbr_nr ? attr->mode : 0;
+}
+
static struct attribute_group group_events_td = {
.name = "events",
};
@@ -4425,10 +4431,23 @@ static struct attribute_group group_events_tsx = {
.is_visible = tsx_is_visible,
};
+static struct attribute_group group_caps_gen = {
+ .name = "caps",
+ .attrs = intel_pmu_caps_attrs,
+};
+
+static struct attribute_group group_caps_lbr = {
+ .name = "caps",
+ .attrs = lbr_attrs,
+ .is_visible = lbr_is_visible,
+};
+
static const struct attribute_group *attr_update[] = {
&group_events_td,
&group_events_mem,
&group_events_tsx,
+ &group_caps_gen,
+ &group_caps_lbr,
NULL,
};
@@ -5055,12 +5074,8 @@ __init int intel_pmu_init(void)
x86_pmu.lbr_nr = 0;
}
- x86_pmu.caps_attrs = intel_pmu_caps_attrs;
-
- if (x86_pmu.lbr_nr) {
- x86_pmu.caps_attrs = merge_attr(x86_pmu.caps_attrs, lbr_attrs);
+ if (x86_pmu.lbr_nr)
pr_cont("%d-deep LBR, ", x86_pmu.lbr_nr);
- }
/*
* Access extra MSR may cause #GP under certain circumstances.
diff --git a/arch/x86/events/perf_event.h b/arch/x86/events/perf_event.h
index 629b313d8b8b..1da9b6f0b279 100644
--- a/arch/x86/events/perf_event.h
+++ b/arch/x86/events/perf_event.h
@@ -631,7 +631,6 @@ struct x86_pmu {
int attr_rdpmc_broken;
int attr_rdpmc;
struct attribute **format_attrs;
- struct attribute **caps_attrs;
ssize_t (*events_sysfs_show)(char *page, u64 config);
const struct attribute_group **attr_update;
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