| lists.openwall.net | lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC | |
|
Open Source and information security mailing list archives
| ||
|
Message-ID: <20190604153120.zcxfn4kh2qjfktgo@core.my.home>
Date: Tue, 4 Jun 2019 17:31:20 +0200
From: Ondřej Jirman <megous@...ous.com>
To: Jernej Škrabec <jernej.skrabec@...il.com>
Cc: linux-sunxi@...glegroups.com,
Maxime Ripard <maxime.ripard@...tlin.com>,
Michael Turquette <mturquette@...libre.com>,
open list <linux-kernel@...r.kernel.org>,
Stephen Boyd <sboyd@...nel.org>, Chen-Yu Tsai <wens@...e.org>,
"open list:COMMON CLK FRAMEWORK" <linux-clk@...r.kernel.org>,
"moderated list:ARM/Allwinner sunXi SoC support"
<linux-arm-kernel@...ts.infradead.org>
Subject: Re: [linux-sunxi] [PATCH] clk: sunxi-ng: sun50i-h6-r: Fix incorrect
W1 clock gate register
Hi Jernej,
On Tue, Jun 04, 2019 at 05:03:55PM +0200, Jernej Škrabec wrote:
> Dne torek, 04. junij 2019 ob 17:00:54 CEST je megous via linux-sunxi
> napisal(a):
> > From: Ondrej Jirman <megous@...ous.com>
> >
> > The current code defines W1 clock gate to be at 0x1cc, overlaying it
> > with the IR gate.
> >
> > Clock gate for r-apb1-w1 is at 0x1ec. This fixes issues with IR receiver
> > causing interrupt floods on H6 (because interrupt flags can't be cleared,
> > due to IR module's bus being disabled).
> >
> > Signed-off-by: Ondrej Jirman <megous@...ous.com>
>
> You should add Fixes tag and CC stable with this.
Not necessary, since H6 IR is not yet supported on mainline.
regards,
o.
> Best regards,
> Jernej
>
>
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel@...ts.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
Powered by blists - more mailing lists