linux-kernel - Re: [PATCH 2/2] pinctrl: qcom: Add SM8150 pinctrl driver

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Message-ID: <20190617062631.GH2962@vkoul-mobl>
Date:   Mon, 17 Jun 2019 11:56:31 +0530
From:   Vinod Koul <vkoul@...nel.org>
To:     Bjorn Andersson <bjorn.andersson@...aro.org>
Cc:     Linus Walleij <linus.walleij@...aro.org>,
        linux-arm-msm@...r.kernel.org,
        Prasad Sodagudi <psodagud@...eaurora.org>,
        Andy Gross <agross@...nel.org>,
        David Brown <david.brown@...aro.org>,
        linux-kernel@...r.kernel.org, linux-gpio@...r.kernel.org,
        "Isaac J . Manjarres" <isaacm@...eaurora.org>
Subject: Re: [PATCH 2/2] pinctrl: qcom: Add SM8150 pinctrl driver

On 16-06-19, 21:17, Bjorn Andersson wrote:
> On Thu 13 Jun 22:30 PDT 2019, Vinod Koul wrote:
> 
> > From: Prasad Sodagudi <psodagud@...eaurora.org>
> > 
> > Add initial pinctrl driver to support pin configuration with
> > pinctrl framework for SM8150
> > 
> > Signed-off-by: Prasad Sodagudi <psodagud@...eaurora.org>
> > Signed-off-by: Isaac J. Manjarres <isaacm@...eaurora.org>
> 
> I presume you did stuff to make it fit with my upstream tiling, mention
> that here.

Thanks for pointing I did miss the changes I did

> 
> [..]
> > diff --git a/drivers/pinctrl/qcom/pinctrl-sm8150.c b/drivers/pinctrl/qcom/pinctrl-sm8150.c
> [..]
> > +static const struct pinctrl_pin_desc sm8150_pins[] = {
> [..]
> > +	PINCTRL_PIN(178, "UFS_RESET"),
> 
> Please follow
> https://lore.kernel.org/linux-arm-msm/20190606010249.3538-2-bjorn.andersson@linaro.org/
> for ufs_reset.

Sure will update 
> 
> > +};
> [..]
> > +enum sm8150_functions {
> > +	msm_mux_phase_flag8,
> 
> Please sort these alphabetically and please squash all the phase_flag*
> into msm_mux_phase_flag.

Will do, is there a reason why we want to squash them?
> 
> > +	msm_mux_phase_flag7,
> > +	msm_mux_emac_pps,
> > +	msm_mux_qup12,
> > +	msm_mux_qup16,
> > +	msm_mux_tsif1_clk,
> 
> Please squash all tsif1 into msm_mux_tsif1.

Will do

> 
> > +	msm_mux_qup8,
> > +	msm_mux_qspi_cs,
> > +	msm_mux_tgu_ch3,
> > +	msm_mux_tsif1_en,
> > +	msm_mux_qspi0,
> > +	msm_mux_mdp_vsync0,
> > +	msm_mux_mdp_vsync1,
> > +	msm_mux_mdp_vsync2,
> > +	msm_mux_mdp_vsync3,
> > +	msm_mux_tgu_ch0,
> > +	msm_mux_tsif1_data,
> > +	msm_mux_qspi1,
> > +	msm_mux_sdc4_cmd,
> 
> Squash sdc4_cmd, sdc4_clk and sdc4{0,1,2,3} into msm_mux_sdc4.

Sure will do on all and again what is the motivation. I am trying to
understand the reasoning so that next time I know what to do :-)

> > +static const struct msm_function sm8150_functions[] = {
> > +	FUNCTION(phase_flag8),
> 
> Please sort this array as well.

okay

> > +static const struct msm_pingroup sm8150_groups[] = {
> [..]
> > +	[58] = PINGROUP(58, SOUTH, qup17, qup19, qdss_cti, qdss_cti, _, _, _, _, _),
> 
> qdss_cti can't be both function 3 and 4 of a single pin.

Let me check, maybe error in downstream code

> > +static struct platform_driver sm8150_pinctrl_driver = {
> > +	.driver = {
> > +		.name = "sm8150-pinctrl",
> > +		.owner = THIS_MODULE,
> 
> No .owner in platform_driver

Yeah missed to remove

-- 
~Vinod