[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <7215e7f2-b8d3-999e-427b-428282765276@huawei.com>
Date: Mon, 17 Jun 2019 16:36:32 +0800
From: Hanjun Guo <guohanjun@...wei.com>
To: Jeremy Linton <jeremy.linton@....com>,
<linux-arm-kernel@...ts.infradead.org>
CC: <linux-acpi@...r.kernel.org>, <linux-kernel@...r.kernel.org>,
<catalin.marinas@....com>, <will.deacon@....com>,
<rjw@...ysocki.net>, <lenb@...nel.org>, <mark.rutland@....com>,
<lorenzo.pieralisi@....com>, <sudeep.holla@....com>
Subject: Re: [PATCH v4 0/4] arm64: SPE ACPI enablement
On 2019/6/15 9:09, Jeremy Linton wrote:
> This patch series enables the Arm Statistical Profiling
> Extension (SPE) on ACPI platforms.
>
> This is possible because ACPI 6.3 uses a previously
> reserved field in the MADT to store the SPE interrupt
> number, similarly to how the normal PMU is described.
> If a consistent valid interrupt exists across all the
> cores in the system, a platform device is registered.
> That then triggers the SPE module, which runs as normal.
>
> We also add the ability to parse the PPTT for IDENTICAL
> cores. We then use this to sanity check the single SPE
> device we create. This creates a bit of a problem with
> respect to the specification though. The specification
> says that its legal for multiple tree's to exist in the
> PPTT. We handle this fine, but what happens in the
> case of multiple tree's is that the lack of a common
> node with IDENTICAL set forces us to assume that there
> are multiple non-IDENTICAL cores in the machine.
>
> v3->v4: Rebase to 5.2.
> Minor formatting, patch rearrangement.
> Add missing `inline` in static header definition.
> Drop ARM_SPE_ACPI and just use ARM_SPE_PMU.
Tested on top of 5.2-rc1, I can see in the boot log:
arm_spe_pmu arm,spe-v1: probed for CPUs 0-95 [max_record_sz 128, align 4, features 0x7]
and I also tested perf record, and works as expected,
Tested-by: Hanjun Guo <guohanjun@...wei.com>
Thanks
Hanjun
Powered by blists - more mailing lists