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Date: Thu, 20 Jun 2019 04:38:38 -0700
From: tip-bot for Fenghua Yu <tipbot@...or.com>
To: linux-tip-commits@...r.kernel.org
Cc: fenghua.yu@...el.com, bp@...e.de, robert.hu@...ux.intel.com,
Thomas.Lendacky@....com, chang.seok.bae@...el.com,
pasha.tatashin@...cle.com, linux-kernel@...r.kernel.org,
tglx@...utronix.de, frederic@...nel.org, mpe@...erman.id.au,
mingo@...nel.org, hpa@...or.com, jannh@...gle.com,
pfeiner@...gle.com, rafael.j.wysocki@...el.com,
sean.j.christopherson@...el.com, x86@...nel.org,
yamada.masahiro@...ionext.com, mingo@...hat.com,
pbonzini@...hat.com, ravi.v.shankar@...el.com, namit@...are.com,
rkrcmar@...hat.com
Subject: [tip:x86/cpu] x86/cpufeatures: Enumerate the new AVX512 BFLOAT16
instructions
Commit-ID: b302e4b176d00e1cbc80148c5d0aee36751f7480
Gitweb: https://git.kernel.org/tip/b302e4b176d00e1cbc80148c5d0aee36751f7480
Author: Fenghua Yu <fenghua.yu@...el.com>
AuthorDate: Mon, 17 Jun 2019 11:00:16 -0700
Committer: Borislav Petkov <bp@...e.de>
CommitDate: Thu, 20 Jun 2019 12:38:49 +0200
x86/cpufeatures: Enumerate the new AVX512 BFLOAT16 instructions
AVX512 BFLOAT16 instructions support 16-bit BFLOAT16 floating-point
format (BF16) for deep learning optimization.
BF16 is a short version of 32-bit single-precision floating-point
format (FP32) and has several advantages over 16-bit half-precision
floating-point format (FP16). BF16 keeps FP32 accumulation after
multiplication without loss of precision, offers more than enough
range for deep learning training tasks, and doesn't need to handle
hardware exception.
AVX512 BFLOAT16 instructions are enumerated in CPUID.7.1:EAX[bit 5]
AVX512_BF16.
CPUID.7.1:EAX contains only feature bits. Reuse the currently empty
word 12 as a pure features word to hold the feature bits including
AVX512_BF16.
Detailed information of the CPUID bit and AVX512 BFLOAT16 instructions
can be found in the latest Intel Architecture Instruction Set Extensions
and Future Features Programming Reference.
[ bp: Check CPUID(7) subleaf validity before accessing subleaf 1. ]
Signed-off-by: Fenghua Yu <fenghua.yu@...el.com>
Signed-off-by: Borislav Petkov <bp@...e.de>
Cc: "Chang S. Bae" <chang.seok.bae@...el.com>
Cc: Frederic Weisbecker <frederic@...nel.org>
Cc: "H. Peter Anvin" <hpa@...or.com>
Cc: Ingo Molnar <mingo@...hat.com>
Cc: Jann Horn <jannh@...gle.com>
Cc: Masahiro Yamada <yamada.masahiro@...ionext.com>
Cc: Michael Ellerman <mpe@...erman.id.au>
Cc: Nadav Amit <namit@...are.com>
Cc: Paolo Bonzini <pbonzini@...hat.com>
Cc: Pavel Tatashin <pasha.tatashin@...cle.com>
Cc: Peter Feiner <pfeiner@...gle.com>
Cc: Radim Krcmar <rkrcmar@...hat.com>
Cc: "Rafael J. Wysocki" <rafael.j.wysocki@...el.com>
Cc: "Ravi V Shankar" <ravi.v.shankar@...el.com>
Cc: Robert Hoo <robert.hu@...ux.intel.com>
Cc: "Sean J Christopherson" <sean.j.christopherson@...el.com>
Cc: Thomas Gleixner <tglx@...utronix.de>
Cc: Thomas Lendacky <Thomas.Lendacky@....com>
Cc: x86 <x86@...nel.org>
Link: https://lkml.kernel.org/r/1560794416-217638-3-git-send-email-fenghua.yu@intel.com
---
arch/x86/include/asm/cpufeature.h | 2 +-
arch/x86/include/asm/cpufeatures.h | 3 +++
arch/x86/kernel/cpu/common.c | 6 ++++++
arch/x86/kernel/cpu/cpuid-deps.c | 1 +
4 files changed, 11 insertions(+), 1 deletion(-)
diff --git a/arch/x86/include/asm/cpufeature.h b/arch/x86/include/asm/cpufeature.h
index 403f70c2e431..58acda503817 100644
--- a/arch/x86/include/asm/cpufeature.h
+++ b/arch/x86/include/asm/cpufeature.h
@@ -23,7 +23,7 @@ enum cpuid_leafs
CPUID_7_0_EBX,
CPUID_D_1_EAX,
CPUID_LNX_4,
- CPUID_DUMMY,
+ CPUID_7_1_EAX,
CPUID_8000_0008_EBX,
CPUID_6_EAX,
CPUID_8000_000A_EDX,
diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h
index be858b86023a..8ecd9fac97c3 100644
--- a/arch/x86/include/asm/cpufeatures.h
+++ b/arch/x86/include/asm/cpufeatures.h
@@ -282,6 +282,9 @@
#define X86_FEATURE_CQM_MBM_TOTAL (11*32+ 2) /* LLC Total MBM monitoring */
#define X86_FEATURE_CQM_MBM_LOCAL (11*32+ 3) /* LLC Local MBM monitoring */
+/* Intel-defined CPU features, CPUID level 0x00000007:1 (EAX), word 12 */
+#define X86_FEATURE_AVX512_BF16 (12*32+ 5) /* AVX512 BFLOAT16 instructions */
+
/* AMD-defined CPU features, CPUID level 0x80000008 (EBX), word 13 */
#define X86_FEATURE_CLZERO (13*32+ 0) /* CLZERO instruction */
#define X86_FEATURE_IRPERF (13*32+ 1) /* Instructions Retired Count */
diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c
index efb114298cfb..dad20bc891d5 100644
--- a/arch/x86/kernel/cpu/common.c
+++ b/arch/x86/kernel/cpu/common.c
@@ -847,6 +847,12 @@ void get_cpu_cap(struct cpuinfo_x86 *c)
c->x86_capability[CPUID_7_0_EBX] = ebx;
c->x86_capability[CPUID_7_ECX] = ecx;
c->x86_capability[CPUID_7_EDX] = edx;
+
+ /* Check valid sub-leaf index before accessing it */
+ if (eax >= 1) {
+ cpuid_count(0x00000007, 1, &eax, &ebx, &ecx, &edx);
+ c->x86_capability[CPUID_7_1_EAX] = eax;
+ }
}
/* Extended state features: level 0x0000000d */
diff --git a/arch/x86/kernel/cpu/cpuid-deps.c b/arch/x86/kernel/cpu/cpuid-deps.c
index fa07a224e7b9..a444028d8145 100644
--- a/arch/x86/kernel/cpu/cpuid-deps.c
+++ b/arch/x86/kernel/cpu/cpuid-deps.c
@@ -62,6 +62,7 @@ static const struct cpuid_dep cpuid_deps[] = {
{ X86_FEATURE_CQM_OCCUP_LLC, X86_FEATURE_CQM_LLC },
{ X86_FEATURE_CQM_MBM_TOTAL, X86_FEATURE_CQM_LLC },
{ X86_FEATURE_CQM_MBM_LOCAL, X86_FEATURE_CQM_LLC },
+ { X86_FEATURE_AVX512_BF16, X86_FEATURE_AVX512VL },
{}
};
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