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Message-ID: <20190624153820.GH29120@arrakis.emea.arm.com>
Date: Mon, 24 Jun 2019 16:38:20 +0100
From: Catalin Marinas <catalin.marinas@....com>
To: Guo Ren <guoren@...nel.org>
Cc: Julien Grall <julien.grall@....com>, linux-kernel@...r.kernel.org,
linux-arm-kernel@...ts.infradead.org, kvmarm@...ts.cs.columbia.edu,
aou@...s.berkeley.edu, gary@...yguo.net,
Atish Patra <Atish.Patra@....com>, hch@...radead.org,
paul.walmsley@...ive.com, rppt@...ux.ibm.com,
linux-riscv@...ts.infradead.org, Anup Patel <anup.Patel@....com>,
Palmer Dabbelt <palmer@...ive.com>, suzuki.poulose@....com,
Marc Zyngier <marc.zyngier@....com>, julien.thierry@....com,
Will Deacon <will.deacon@....com>, christoffer.dall@....com,
james.morse@....com
Subject: Re: [PATCH RFC 11/14] arm64: Move the ASID allocator code in a
separate file
On Mon, Jun 24, 2019 at 12:35:35AM +0800, Guo Ren wrote:
> On Fri, Jun 21, 2019 at 10:16 PM Catalin Marinas
> <catalin.marinas@....com> wrote:
> > BTW, if you find the algorithm fairly straightforward ;), see this
> > bug-fix which took a formal model to identify: a8ffaaa060b8 ("arm64:
> > asid: Do not replace active_asids if already 0").
[...]
> Btw, Is this detected by arm's aisd allocator TLA+ model ? Or a real
> bug report ?
This specific bug was found by the TLA+ model checker (at the time we
were actually tracking down another bug with multi-threaded CPU sharing
the TLB, bug also confirmed by the formal model).
--
Catalin
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