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Message-ID: <CACPK8XcPxJAOBAnKMKxtiG4Fkz8BPf8KtW1Kc3A9tU_emQviVg@mail.gmail.com>
Date: Thu, 27 Jun 2019 03:30:35 +0000
From: Joel Stanley <joel@....id.au>
To: Andrew Jeffery <andrew@...id.au>
Cc: linux-gpio@...r.kernel.org, Ryan Chen <ryan_chen@...eedtech.com>,
Linus Walleij <linus.walleij@...aro.org>,
Rob Herring <robh+dt@...nel.org>,
Mark Rutland <mark.rutland@....com>,
linux-aspeed@...ts.ozlabs.org,
OpenBMC Maillist <openbmc@...ts.ozlabs.org>,
devicetree <devicetree@...r.kernel.org>,
Linux ARM <linux-arm-kernel@...ts.infradead.org>,
Linux Kernel Mailing List <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH 5/8] pinctrl: aspeed: Correct comment that is no longer true
On Wed, 26 Jun 2019 at 07:16, Andrew Jeffery <andrew@...id.au> wrote:
>
> We have handled the GFX register case for quite some time now.
>
> Signed-off-by: Andrew Jeffery <andrew@...id.au>
> ---
> drivers/pinctrl/aspeed/pinctrl-aspeed.h | 3 +--
> 1 file changed, 1 insertion(+), 2 deletions(-)
>
> diff --git a/drivers/pinctrl/aspeed/pinctrl-aspeed.h b/drivers/pinctrl/aspeed/pinctrl-aspeed.h
> index 4b06ddbc6aec..c5918c4a087c 100644
> --- a/drivers/pinctrl/aspeed/pinctrl-aspeed.h
> +++ b/drivers/pinctrl/aspeed/pinctrl-aspeed.h
> @@ -240,8 +240,7 @@
> * opposed to naming them e.g. PINMUX_CTRL_[0-9]). Further, signal expressions
> * reference registers beyond those dedicated to pinmux, such as the system
> * reset control and MAC clock configuration registers. The AST2500 goes a step
AST2600 too?
Acked-by: Joel Stanley <joel@....id.au>
> - * further and references registers in the graphics IP block, but that isn't
> - * handled yet.
> + * further and references registers in the graphics IP block.
> */
> #define SCU2C 0x2C /* Misc. Control Register */
> #define SCU3C 0x3C /* System Reset Control/Status Register */
> --
> 2.20.1
>
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