linux-kernel - [PATCH v1 37/50] ARM: dts: exynos: change parent and rate of bus

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite for Android: free password hash cracker in your pocket

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Date:   Mon, 15 Jul 2019 14:44:04 +0200
From:   Lukasz Luba <l.luba@...tner.samsung.com>
To:     devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
        linux-arm-kernel@...ts.infradead.org,
        linux-samsung-soc@...r.kernel.org, linux-clk@...r.kernel.org
Cc:     mturquette@...libre.com, sboyd@...nel.org,
        b.zolnierkie@...sung.com, krzk@...nel.org, kgene@...nel.org,
        mark.rutland@....com, robh+dt@...nel.org, cw00.choi@...sung.com,
        kyungmin.park@...sung.com, a.hajda@...sung.com,
        m.szyprowski@...sung.com, s.nawrocki@...sung.com,
        myungjoo.ham@...sung.com, Lukasz Luba <l.luba@...tner.samsung.com>
Subject: [PATCH v1 37/50] ARM: dts: exynos: change parent and rate of
 bus_fsys in Exynos5422

The FSYS bus OPP table has been aligned to the new parent rate. This patch
sets the proper parent and picks the init frequency before the devfreq
governor starts working. It sets also parent rate (DPLL to 1200MHz).

Signed-off-by: Lukasz Luba <l.luba@...tner.samsung.com>
---
 arch/arm/boot/dts/exynos5422-odroid-core.dtsi | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi
index d460041f716c..6a82dd175b8a 100644
--- a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi
+++ b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi
@@ -72,6 +72,11 @@
 
 &bus_fsys {
 	devfreq = <&bus_wcore>;
+	assigned-clocks = <&clock CLK_MOUT_ACLK200_FSYS>,
+			  <&clock CLK_DOUT_ACLK200_FSYS>,
+			  <&clock CLK_FOUT_DPLL>;
+	assigned-clock-parents = <&clock CLK_MOUT_SCLK_DPLL>;
+	assigned-clock-rates = <0>, <240000000>,<1200000000>;
 	status = "okay";
 };
 
-- 
2.17.1