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Message-ID: <CAJKOXPdGnyEayFBuNPgrdB-9oqdvxkRCLm93kDBVfHnmnAgc9g@mail.gmail.com>
Date: Wed, 17 Jul 2019 12:35:01 +0200
From: Krzysztof Kozlowski <krzk@...nel.org>
To: Lukasz Luba <l.luba@...tner.samsung.com>
Cc: devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
linux-arm-kernel@...ts.infradead.org,
"linux-samsung-soc@...r.kernel.org"
<linux-samsung-soc@...r.kernel.org>, linux-clk@...r.kernel.org,
mturquette@...libre.com, sboyd@...nel.org,
Bartłomiej Żołnierkiewicz
<b.zolnierkie@...sung.com>, kgene@...nel.org, mark.rutland@....com,
robh+dt@...nel.org, Chanwoo Choi <cw00.choi@...sung.com>,
kyungmin.park@...sung.com, Andrzej Hajda <a.hajda@...sung.com>,
Marek Szyprowski <m.szyprowski@...sung.com>,
s.nawrocki@...sung.com, myungjoo.ham@...sung.com
Subject: Re: [PATCH v1 33/50] ARM: dts: exynos: set parent clocks to UARTs in Exynos5420
On Mon, 15 Jul 2019 at 14:45, Lukasz Luba <l.luba@...tner.samsung.com> wrote:
>
> Change the parents of UART clocks to the CPLL which has 666MHz.
> The UARTs' dividers use /10 rate so they would have 66.6MHz.
Write also the state before to show what is being fixed (I assume
previous frequency was not best choice).
BR,
Krzysztof
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