linux-kernel - Re: [PATCH V5 11/18] clk: tegra210: Add support for Tegra210 clocks

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Message-ID: <5c6e17ed-bdbd-fa27-87e7-aa95dfa7c591@gmail.com>
Date:   Thu, 18 Jul 2019 23:11:48 +0300
From:   Dmitry Osipenko <digetx@...il.com>
To:     Sowjanya Komatineni <skomatineni@...dia.com>,
        Peter De Schrijver <pdeschrijver@...dia.com>
Cc:     Joseph Lo <josephl@...dia.com>, thierry.reding@...il.com,
        jonathanh@...dia.com, tglx@...utronix.de, jason@...edaemon.net,
        marc.zyngier@....com, linus.walleij@...aro.org, stefan@...er.ch,
        mark.rutland@....com, pgaikwad@...dia.com, sboyd@...nel.org,
        linux-clk@...r.kernel.org, linux-gpio@...r.kernel.org,
        jckuo@...dia.com, talho@...dia.com, linux-tegra@...r.kernel.org,
        linux-kernel@...r.kernel.org, mperttunen@...dia.com,
        spatra@...dia.com, robh+dt@...nel.org, devicetree@...r.kernel.org
Subject: Re: [PATCH V5 11/18] clk: tegra210: Add support for Tegra210 clocks

18.07.2019 22:24, Sowjanya Komatineni пишет:
> 
> On 7/18/19 12:18 PM, Peter De Schrijver wrote:
>> On Tue, Jul 16, 2019 at 09:43:16PM +0300, Dmitry Osipenko wrote:
>>>> CPU parents are PLL_X, PLL_P, and dfll. PLL_X always runs at higher
>>>> rate
>>>> so switching to PLL_P during CPUFreq probe prior to dfll clock enable
>>>> should be safe.
>>> AFAIK, PLLX could run at ~200MHz. There is also a divided output of PLLP
>>> which CCLKG supports, the PLLP_OUT4.
>>>
>>> Probably, realistically, CPU is always running off a fast PLLX during
>>> boot, but I'm wondering what may happen on KEXEC. I guess ideally
>>> CPUFreq driver should also have a 'shutdown' callback to teardown DFLL
>>> on a reboot, but likely that there are other clock-related problems as
>>> well that may break KEXEC and thus it is not very important at the
>>> moment.
>>>
>> If you turn off the DFLL, you have to be aware that the voltage margins
>> for DFLL use are lower than for PLL use. So you either need to be sure
>> to switch to a frequency below fmax @ Vmin or you program the boot
>> voltage and then you can use PLLX as setup by the bootloader. For OVR
>> regulators you can't program a voltage without the DFLL, so you have to
>> tristate the PWM output which will give you a hardwired boot voltage.
>>
>> Peter.
> 
> Yes, we switch CPU to PLLP and then disable DFLL during suspend.

I'm wondering what happens to T124 on resume from suspend, given that it
switches CPU to PLLX [1]. I imagine that CPU voltage could be lower than
needed if suspend happened on DFLL. I'm also now vaguely recalling that
CPUFreq driver was disabled for T124 because of some problems.

Or maybe warmboot code is actually touching the voltage regulators?

[1]
https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/tree/arch/arm/mach-tegra/sleep-tegra30.S#n389

That is also should be a problem for T30 if voltage scaling is happening
and I have some patches in works that are switching CPU to PLLP instead
of PLLX on suspend/resume.