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Message-Id: <20190722220514.C53FE21951@mail.kernel.org>
Date: Mon, 22 Jul 2019 15:05:13 -0700
From: Stephen Boyd <sboyd@...nel.org>
To: Geert Uytterhoeven <geert+renesas@...der.be>,
Michael Turquette <mturquette@...libre.com>
Cc: Yao Lihua <Lihua.Yao@...ay-svautomotive.com>,
Yoshihiro Shimoda <yoshihiro.shimoda.uh@...esas.com>,
Wolfram Sang <wsa+renesas@...g-engineering.com>,
linux-clk@...r.kernel.org, linux-renesas-soc@...r.kernel.org,
linux-kernel@...r.kernel.org,
Geert Uytterhoeven <geert+renesas@...der.be>
Subject: Re: [PATCH] clk: renesas: cpg-mssr: Fix reset control race condition
Quoting Geert Uytterhoeven (2019-07-11 06:03:59)
> The module reset code in the Renesas CPG/MSSR driver uses
> read-modify-write (RMW) operations to write to a Software Reset Register
> (SRCRn), and simple writes to write to a Software Reset Clearing
> Register (SRSTCLRn), as was mandated by the R-Car Gen2 and Gen3 Hardware
> User's Manuals.
>
> However, this may cause a race condition when two devices are reset in
> parallel: if the reset for device A completes in the middle of the RMW
> operation for device B, device A may be reset again, causing subtle
> failures (e.g. i2c timeouts):
>
> thread A thread B
> -------- --------
Applied to clk-fixes
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