linux-kernel - Re: [PATCH v1 21/50] ARM: dts: exynos: add OPP into FSYS APB bus in Exynos5420

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <7b662b86-f442-3de8-e357-88bf9eaffd5a@partner.samsung.com>
Date:   Mon, 22 Jul 2019 12:47:00 +0200
From:   Lukasz Luba <l.luba@...tner.samsung.com>
To:     Krzysztof Kozlowski <krzk@...nel.org>
Cc:     devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
        linux-arm-kernel@...ts.infradead.org,
        "linux-samsung-soc@...r.kernel.org" 
        <linux-samsung-soc@...r.kernel.org>, linux-clk@...r.kernel.org,
        mturquette@...libre.com, sboyd@...nel.org,
        Bartłomiej Żołnierkiewicz 
        <b.zolnierkie@...sung.com>, kgene@...nel.org, mark.rutland@....com,
        robh+dt@...nel.org, Chanwoo Choi <cw00.choi@...sung.com>,
        kyungmin.park@...sung.com, Andrzej Hajda <a.hajda@...sung.com>,
        Marek Szyprowski <m.szyprowski@...sung.com>,
        s.nawrocki@...sung.com, myungjoo.ham@...sung.com
Subject: Re: [PATCH v1 21/50] ARM: dts: exynos: add OPP into FSYS APB bus in
 Exynos5420

Hi Krzysztof,

On 7/17/19 10:48 AM, Krzysztof Kozlowski wrote:
> On Mon, 15 Jul 2019 at 14:44, Lukasz Luba <l.luba@...tner.samsung.com> wrote:
>>
>> Add an OPP for FSYS APB which reflects the real possible frequency.
>> The bus will have a new parent clock which speed has 600MHz, thus
>> a new possible frequency provided by the clock divider is 150MHz.
>> According to the documentation max possible frequency for this bus is
>> 200MHz.
> 
> Commit msg is good but title could be improved. Focus in the title
> what problem/issue you are solving - add intermediate step in scaling
> of FSYS APB?
The devfreq governor for this bus device follows the set OPP of the
master device - WCORE bus and sets the OPP with corresponding ID.
Thus, jumping to max frequency 200MHz when the WCORE bus and other
devices are operating in the middle of their min-max speed is not
needed for FSYS APB and this patch adds the intermediate speed step.

Regards,
Lukasz

> 
> Best regards,
> Krzysztof
> 
>