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Message-ID: <AM0PR04MB44815D9F3B2ABC00D0CF311288C70@AM0PR04MB4481.eurprd04.prod.outlook.com>
Date:   Tue, 23 Jul 2019 00:56:47 +0000
From:   Peng Fan <peng.fan@....com>
To:     Stephen Boyd <sboyd@...nel.org>,
        "festevam@...il.com" <festevam@...il.com>,
        "kernel@...gutronix.de" <kernel@...gutronix.de>,
        "mturquette@...libre.com" <mturquette@...libre.com>,
        "s.hauer@...gutronix.de" <s.hauer@...gutronix.de>,
        "shawnguo@...nel.org" <shawnguo@...nel.org>
CC:     dl-linux-imx <linux-imx@....com>,
        Leonard Crestez <leonard.crestez@....com>,
        Anson Huang <anson.huang@....com>,
        Jacky Bai <ping.bai@....com>,
        "linux-clk@...r.kernel.org" <linux-clk@...r.kernel.org>,
        "linux-arm-kernel@...ts.infradead.org" 
        <linux-arm-kernel@...ts.infradead.org>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        "van.freenix@...il.com" <van.freenix@...il.com>,
        "stable@...r.kernel.org" <stable@...r.kernel.org>
Subject: RE: [PATCH] clk: imx: imx8mm: fix audio pll setting

Hi Stephen,

> Subject: Re: [PATCH] clk: imx: imx8mm: fix audio pll setting
> 
> Quoting Peng Fan (2019-07-14 19:55:43)
> > From: Peng Fan <peng.fan@....com>
> >
> > The AUDIO PLL max support 650M, so the original clk settings violate
> > spec. This patch makes the output 786432000 -> 393216000, and
> > 722534400 -> 361267200 to aligned with NXP vendor kernel without any
> > impact on audio functionality and go within 650MHz PLL limit.
> >
> > Cc: <stable@...r.kernel.org>
> > Fixes: ba5625c3e272 ("clk: imx: Add clock driver support for imx8mm")
> > Signed-off-by: Peng Fan <peng.fan@....com>
> > ---
> 
> Is this a problem right now, i.e. should I apply this to clk-fixes? Or can this wait
> until next merge window?

Could wait until next merge window.

Thanks,
Peng.

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