linux-kernel - [tip:perf/urgent] perf/x86/intel: Fix SLOTS PEBS event constraint

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Message-ID: <tip-3d0c3953601d250175c7684ec0d9df612061dae5@git.kernel.org>
Date:   Thu, 25 Jul 2019 09:05:37 -0700
From:   tip-bot for Kan Liang <tipbot@...or.com>
To:     linux-tip-commits@...r.kernel.org
Cc:     ak@...ux.intel.com, torvalds@...ux-foundation.org,
        kan.liang@...ux.intel.com, hpa@...or.com, peterz@...radead.org,
        mingo@...nel.org, linux-kernel@...r.kernel.org, tglx@...utronix.de
Subject: [tip:perf/urgent] perf/x86/intel: Fix SLOTS PEBS event constraint

Commit-ID:  3d0c3953601d250175c7684ec0d9df612061dae5
Gitweb:     https://git.kernel.org/tip/3d0c3953601d250175c7684ec0d9df612061dae5
Author:     Kan Liang <kan.liang@...ux.intel.com>
AuthorDate: Tue, 23 Jul 2019 13:04:29 -0700
Committer:  Ingo Molnar <mingo@...nel.org>
CommitDate: Thu, 25 Jul 2019 15:41:29 +0200

perf/x86/intel: Fix SLOTS PEBS event constraint

Sampling SLOTS event and ref-cycles event in a group on Icelake gives
EINVAL.

SLOTS event is the event stands for the fixed counter 3, not fixed
counter 2. Wrong mask was set to SLOTS event in
intel_icl_pebs_event_constraints[].

Reported-by: Andi Kleen <ak@...ux.intel.com>
Signed-off-by: Kan Liang <kan.liang@...ux.intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@...radead.org>
Cc: Linus Torvalds <torvalds@...ux-foundation.org>
Cc: Peter Zijlstra <peterz@...radead.org>
Cc: Thomas Gleixner <tglx@...utronix.de>
Fixes: 6017608936c1 ("perf/x86/intel: Add Icelake support")
Link: https://lkml.kernel.org/r/20190723200429.8180-1-kan.liang@linux.intel.com
Signed-off-by: Ingo Molnar <mingo@...nel.org>
---
 arch/x86/events/intel/ds.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/x86/events/intel/ds.c b/arch/x86/events/intel/ds.c
index 2c8db2c19328..f1269e804e9b 100644
--- a/arch/x86/events/intel/ds.c
+++ b/arch/x86/events/intel/ds.c
@@ -851,7 +851,7 @@ struct event_constraint intel_skl_pebs_event_constraints[] = {
 
 struct event_constraint intel_icl_pebs_event_constraints[] = {
 	INTEL_FLAGS_UEVENT_CONSTRAINT(0x1c0, 0x100000000ULL),	/* INST_RETIRED.PREC_DIST */
-	INTEL_FLAGS_UEVENT_CONSTRAINT(0x0400, 0x400000000ULL),	/* SLOTS */
+	INTEL_FLAGS_UEVENT_CONSTRAINT(0x0400, 0x800000000ULL),	/* SLOTS */
 
 	INTEL_PLD_CONSTRAINT(0x1cd, 0xff),			/* MEM_TRANS_RETIRED.LOAD_LATENCY */
 	INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x1d0, 0xf),	/* MEM_INST_RETIRED.LOAD */