linux-kernel - [tip:perf/urgent] perf/x86/intel: Fix invalid Bit 13 for Icelake MSR_OFFCORE_RSP

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Message-ID: <tip-3b238a64c3009fed36eaea1af629d9377759d87d@git.kernel.org>
Date:   Thu, 25 Jul 2019 09:06:23 -0700
From:   tip-bot for Yunying Sun <tipbot@...or.com>
To:     linux-tip-commits@...r.kernel.org
Cc:     tglx@...utronix.de, mingo@...nel.org, peterz@...radead.org,
        linux-kernel@...r.kernel.org, yunying.sun@...el.com, hpa@...or.com,
        kan.liang@...ux.intel.com, torvalds@...ux-foundation.org
Subject: [tip:perf/urgent] perf/x86/intel: Fix invalid Bit 13 for Icelake
 MSR_OFFCORE_RSP_x register

Commit-ID:  3b238a64c3009fed36eaea1af629d9377759d87d
Gitweb:     https://git.kernel.org/tip/3b238a64c3009fed36eaea1af629d9377759d87d
Author:     Yunying Sun <yunying.sun@...el.com>
AuthorDate: Wed, 24 Jul 2019 16:29:32 +0800
Committer:  Ingo Molnar <mingo@...nel.org>
CommitDate: Thu, 25 Jul 2019 15:41:30 +0200

perf/x86/intel: Fix invalid Bit 13 for Icelake MSR_OFFCORE_RSP_x register

The Intel SDM states that bit 13 of Icelake's MSR_OFFCORE_RSP_x
register is valid, and used for counting hardware generated prefetches
of L3 cache. Update the bitmask to allow bit 13.

Before:
$ perf stat -e cpu/event=0xb7,umask=0x1,config1=0x1bfff/u sleep 3
 Performance counter stats for 'sleep 3':
   <not supported>      cpu/event=0xb7,umask=0x1,config1=0x1bfff/u

After:
$ perf stat -e cpu/event=0xb7,umask=0x1,config1=0x1bfff/u sleep 3
 Performance counter stats for 'sleep 3':
             9,293      cpu/event=0xb7,umask=0x1,config1=0x1bfff/u

Signed-off-by: Yunying Sun <yunying.sun@...el.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@...radead.org>
Reviewed-by: Kan Liang <kan.liang@...ux.intel.com>
Cc: Linus Torvalds <torvalds@...ux-foundation.org>
Cc: Peter Zijlstra <peterz@...radead.org>
Cc: Thomas Gleixner <tglx@...utronix.de>
Cc: acme@...nel.org
Cc: alexander.shishkin@...ux.intel.com
Cc: bp@...en8.de
Cc: hpa@...or.com
Cc: jolsa@...hat.com
Cc: namhyung@...nel.org
Link: https://lkml.kernel.org/r/20190724082932.12833-1-yunying.sun@intel.com
Signed-off-by: Ingo Molnar <mingo@...nel.org>
---
 arch/x86/events/intel/core.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c
index 9e911a96972b..b35519cbc8b4 100644
--- a/arch/x86/events/intel/core.c
+++ b/arch/x86/events/intel/core.c
@@ -263,8 +263,8 @@ static struct event_constraint intel_icl_event_constraints[] = {
 };
 
 static struct extra_reg intel_icl_extra_regs[] __read_mostly = {
-	INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3fffff9fffull, RSP_0),
-	INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0x3fffff9fffull, RSP_1),
+	INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3fffffbfffull, RSP_0),
+	INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0x3fffffbfffull, RSP_1),
 	INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd),
 	INTEL_UEVENT_EXTRA_REG(0x01c6, MSR_PEBS_FRONTEND, 0x7fff17, FE),
 	EVENT_EXTRA_END