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Message-Id: <20190730184256.30338-14-helen.koike@collabora.com>
Date: Tue, 30 Jul 2019 15:42:55 -0300
From: Helen Koike <helen.koike@...labora.com>
To: linux-rockchip@...ts.infradead.org
Cc: devicetree@...r.kernel.org, eddie.cai.linux@...il.com,
mchehab@...nel.org, heiko@...ech.de, jacob2.chen@...k-chips.com,
jeffy.chen@...k-chips.com, zyc@...k-chips.com,
linux-kernel@...r.kernel.org, tfiga@...omium.org,
hans.verkuil@...co.com, laurent.pinchart@...asonboard.com,
sakari.ailus@...ux.intel.com, kernel@...labora.com,
ezequiel@...labora.com, linux-media@...r.kernel.org,
linux-arm-kernel@...ts.infradead.org, zhengsq@...k-chips.com,
Helen Koike <helen.koike@...labora.com>
Subject: [PATCH v8 13/14] arm64: dts: rockchip: add rx0 mipi-phy for rk3399
From: Shunqian Zheng <zhengsq@...k-chips.com>
It's a Designware MIPI D-PHY, used for ISP0 in rk3399.
Signed-off-by: Shunqian Zheng <zhengsq@...k-chips.com>
Signed-off-by: Jacob Chen <jacob2.chen@...k-chips.com>
[update for upstream]
Signed-off-by: Helen Koike <helen.koike@...labora.com>
---
Changes in v8: None
Changes in v7:
- add phy-cells
arch/arm64/boot/dts/rockchip/rk3399.dtsi | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
index 776d2bd48c06..3630d95e5cd8 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
@@ -1385,6 +1385,17 @@
status = "disabled";
};
+ mipi_dphy_rx0: mipi-dphy-rx0 {
+ compatible = "rockchip,rk3399-mipi-dphy";
+ clocks = <&cru SCLK_MIPIDPHY_REF>,
+ <&cru SCLK_DPHY_RX0_CFG>,
+ <&cru PCLK_VIO_GRF>;
+ clock-names = "dphy-ref", "dphy-cfg", "grf";
+ power-domains = <&power RK3399_PD_VIO>;
+ #phy-cells = <0>;
+ status = "disabled";
+ };
+
u2phy0: usb2-phy@...0 {
compatible = "rockchip,rk3399-usb2phy";
reg = <0xe450 0x10>;
--
2.22.0
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