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Message-ID: <MWHPR2201MB1277252B4F5EC00386B604E6C1D50@MWHPR2201MB1277.namprd22.prod.outlook.com>
Date: Tue, 6 Aug 2019 23:02:03 +0000
From: Paul Burton <paul.burton@...s.com>
To: Zhou Yanjie <zhouyanjie@...o.com>
CC: "linux-mips@...r.kernel.org" <linux-mips@...r.kernel.org>,
"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
"ralf@...ux-mips.org" <ralf@...ux-mips.org>,
"paul@...pouillou.net" <paul@...pouillou.net>,
Paul Burton <pburton@...ecomp.com>,
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Subject: Re: [PATCH 1/2 v4] MIPS: Ingenic: Fix bugs when detecting X1000's L2
cache.
Hello,
Zhou Yanjie wrote:
> 1.fix bugs when detecting L2 cache sets value.
> 2.fix bugs when detecting L2 cache ways value.
Series applied to mips-next.
Thanks,
Paul
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