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Date: Mon, 12 Aug 2019 04:22:11 +0000 From: "Z.q. Hou" <zhiqiang.hou@....com> To: "linux-pci@...r.kernel.org" <linux-pci@...r.kernel.org>, "devicetree@...r.kernel.org" <devicetree@...r.kernel.org>, "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>, "gustavo.pimentel@...opsys.com" <gustavo.pimentel@...opsys.com>, "jingoohan1@...il.com" <jingoohan1@...il.com>, "bhelgaas@...gle.com" <bhelgaas@...gle.com>, "robh+dt@...nel.org" <robh+dt@...nel.org>, "mark.rutland@....com" <mark.rutland@....com>, "shawnguo@...nel.org" <shawnguo@...nel.org>, Leo Li <leoyang.li@....com>, "lorenzo.pieralisi@....com" <lorenzo.pieralisi@....com> CC: "M.h. Lian" <minghuan.lian@....com>, "Z.q. Hou" <zhiqiang.hou@....com> Subject: [PATCH 0/4] Layerscape: Remove num-lanes property from PCIe nodes From: Hou Zhiqiang <Zhiqiang.Hou@....com> On FSL Layerscape SoCs, the number of lanes assigned to PCIe controller is not fixed, it is determined by the selected SerDes protocol. The current num-lanes indicates the max lanes PCIe controller can support up to, instead of the lanes assigned to the PCIe controller. This can result in PCIe link training fail after hot-reset. Hou Zhiqiang (4): dt-bingings: PCI: Remove the num-lanes from Required properties PCI: dwc: Return directly when num-lanes is not found ARM: dts: ls1021a: Remove num-lanes property from PCIe nodes arm64: dts: fsl: Remove num-lanes property from PCIe nodes Documentation/devicetree/bindings/pci/designware-pcie.txt | 1 - arch/arm/boot/dts/ls1021a.dtsi | 2 -- arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi | 1 - arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 3 --- arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi | 6 ------ arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi | 3 --- arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi | 4 ---- drivers/pci/controller/dwc/pcie-designware.c | 6 ++++-- 8 files changed, 4 insertions(+), 22 deletions(-) -- 2.17.1
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