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Message-Id: <20190813103759.38358-2-git@andred.net>
Date: Tue, 13 Aug 2019 11:37:59 +0100
From: André Draszik <git@...red.net>
To: linux-kernel@...r.kernel.org
Cc: André Draszik <git@...red.net>,
Richard Zhu <hongxing.zhu@....com>,
Lucas Stach <l.stach@...gutronix.de>,
Bjorn Helgaas <bhelgaas@...gle.com>,
Rob Herring <robh+dt@...nel.org>,
Mark Rutland <mark.rutland@....com>,
Shawn Guo <shawnguo@...nel.org>,
Sascha Hauer <s.hauer@...gutronix.de>,
Pengutronix Kernel Team <kernel@...gutronix.de>,
Fabio Estevam <festevam@...il.com>,
NXP Linux Team <linux-imx@....com>,
linux-pci@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
devicetree@...r.kernel.org
Subject: [PATCH 2/2] dt-bindings: imx6q-pcie: add "fsl,pcie-phy-refclk-internal" for i.MX7D
The i.MX7D variant of the IP can use either an external
crystal oscillator input or an internal clock input as
a reference clock input for the PCIe PHY.
Document the optional property 'fsl,pcie-phy-refclk-internal'
Signed-off-by: André Draszik <git@...red.net>
Cc: Richard Zhu <hongxing.zhu@....com>
Cc: Lucas Stach <l.stach@...gutronix.de>
Cc: Bjorn Helgaas <bhelgaas@...gle.com>
Cc: Rob Herring <robh+dt@...nel.org>
Cc: Mark Rutland <mark.rutland@....com>
Cc: Shawn Guo <shawnguo@...nel.org>
Cc: Sascha Hauer <s.hauer@...gutronix.de>
Cc: Pengutronix Kernel Team <kernel@...gutronix.de>
Cc: Fabio Estevam <festevam@...il.com>
Cc: NXP Linux Team <linux-imx@....com>
Cc: linux-pci@...r.kernel.org
Cc: linux-arm-kernel@...ts.infradead.org
Cc: devicetree@...r.kernel.org
Cc: linux-kernel@...r.kernel.org
---
Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt
index a7f5f5afa0e6..985d7083df9f 100644
--- a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt
+++ b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt
@@ -56,6 +56,11 @@ Additional required properties for imx7d-pcie and imx8mq-pcie:
- "turnoff"
- fsl,imx7d-pcie-phy: A phandle to an fsl,imx7d-pcie-phy node.
+Additional optional properties for imx7d-pcie:
+- fsl,pcie-phy-refclk-internal: If present then an internal PLL input is used
+ as PCIe PHY reference clock source. By default an external ocsillator input
+ is used.
+
Additional required properties for imx8mq-pcie:
- clock-names: Must include the following additional entries:
- "pcie_aux"
--
2.23.0.rc1
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