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Message-Id: <20190814153014.12962-1-dinguyen@kernel.org>
Date: Wed, 14 Aug 2019 10:30:14 -0500
From: Dinh Nguyen <dinguyen@...nel.org>
To: linux-clk@...r.kernel.org
Cc: dinguyen@...nel.org, linux-kernel@...r.kernel.org,
sboyd@...nel.org, mturquette@...libre.com, stable@...r.kernel.org
Subject: [PATCH] clk: socfpga: stratix10: fix rate caclulationg for cnt_clks
Checking bypass_reg is incorrect for calculating the cnt_clk rates.
Instead we should be checking that there is a proper hardware register
that holds the clock divider.
Cc: stable@...r.kernel.org
Signed-off-by: Dinh Nguyen <dinguyen@...nel.org>
---
drivers/clk/socfpga/clk-periph-s10.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/socfpga/clk-periph-s10.c b/drivers/clk/socfpga/clk-periph-s10.c
index 5c50e723ecae..1a191eeeebba 100644
--- a/drivers/clk/socfpga/clk-periph-s10.c
+++ b/drivers/clk/socfpga/clk-periph-s10.c
@@ -38,7 +38,7 @@ static unsigned long clk_peri_cnt_clk_recalc_rate(struct clk_hw *hwclk,
if (socfpgaclk->fixed_div) {
div = socfpgaclk->fixed_div;
} else {
- if (!socfpgaclk->bypass_reg)
+ if (socfpgaclk->hw.reg)
div = ((readl(socfpgaclk->hw.reg) & 0x7ff) + 1);
}
--
2.20.0
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