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Message-Id: <20190814162324.BF27020665@mail.kernel.org>
Date: Wed, 14 Aug 2019 09:23:23 -0700
From: Stephen Boyd <sboyd@...nel.org>
To: Dinh Nguyen <dinguyen@...nel.org>, linux-clk@...r.kernel.org
Cc: dinguyen@...nel.org, linux-kernel@...r.kernel.org,
mturquette@...libre.com, stable@...r.kernel.org
Subject: Re: [PATCH] clk: socfpga: stratix10: fix rate caclulationg for cnt_clks
Quoting Dinh Nguyen (2019-08-14 08:30:14)
> Checking bypass_reg is incorrect for calculating the cnt_clk rates.
> Instead we should be checking that there is a proper hardware register
> that holds the clock divider.
>
> Cc: stable@...r.kernel.org
> Signed-off-by: Dinh Nguyen <dinguyen@...nel.org>
> ---
Applied to clk-fixes
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