linux-kernel - Re: [PATCH 13/15] riscv: clear the instruction cache and all registers when booting

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Message-ID: <20190814043551.GA22862@lst.de>
Date:   Wed, 14 Aug 2019 06:35:51 +0200
From:   Christoph Hellwig <hch@....de>
To:     Alan Kao <alankao@...estech.com>
Cc:     Christoph Hellwig <hch@....de>, Palmer Dabbelt <palmer@...ive.com>,
        Paul Walmsley <paul.walmsley@...ive.com>,
        Damien Le Moal <damien.lemoal@....com>,
        linux-riscv@...ts.infradead.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH 13/15] riscv: clear the instruction cache and all
 registers when booting

On Wed, Aug 14, 2019 at 09:00:14AM +0800, Alan Kao wrote:
> But it doesn't really mean that the running system has an FPU given CONFIG_FPU
> enabled.  Normally the existence of an FPU is checked in riscv_fill_hwcap by
> searching device tree, where the code looks like
> 
> 
> bool has_fpu = false; // this one is global
> ...
> #ifdef CONFIG_FPU
>         if (elf_hwcap & (COMPAT_HWCAP_ISA_F | COMPAT_HWCAP_ISA_D))
>                 has_fpu = true;
> #endif
> 
> 
> Or does CONFIG_FPU have a more intuitive meaning when CONFIG_M_MODE is enabled?

No, it doesn't..

> 
> > +	csrr	t0, CSR_MISA
> > +	andi	t0, t0, (COMPAT_HWCAP_ISA_F | COMPAT_HWCAP_ISA_D)
> > +	bnez	t0, .Lreset_regs_done

... which is why we have these few lines of code that check the
caps returns from the misa CSR, similar to the elf_caps check quoted
above.