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Message-ID: <312b307b-19cc-84f8-97e6-07dbdf07dd12@citrix.com>
Date:   Thu, 15 Aug 2019 22:25:24 +0100
From:   Andrew Cooper <andrew.cooper3@...rix.com>
To:     Borislav Petkov <bp@...en8.de>
CC:     "Lendacky, Thomas" <Thomas.Lendacky@....com>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        "linux-doc@...r.kernel.org" <linux-doc@...r.kernel.org>,
        "linux-pm@...r.kernel.org" <linux-pm@...r.kernel.org>,
        "x86@...nel.org" <x86@...nel.org>,
        Thomas Gleixner <tglx@...utronix.de>,
        Ingo Molnar <mingo@...hat.com>,
        "Rafael J . Wysocki" <rjw@...ysocki.net>,
        Pavel Machek <pavel@....cz>, Chen Yu <yu.c.chen@...el.com>,
        Jonathan Corbet <corbet@....net>
Subject: Re: [PATCH] x86/CPU/AMD: Clear RDRAND CPUID bit on AMD family 15h/16h

On 15/08/2019 22:05, Borislav Petkov wrote:
> On Thu, Aug 15, 2019 at 09:59:03PM +0100, Andrew Cooper wrote:
>> If you're virtualised, the write to MSR_AMD64_CPUID_FN_1 almost
>> certainly won't take effect, which means userspace will still be able to
>> see the bit.
> msr_clear_bit() has a return value. We should check it before
> doing anything further. I hope the HV actually signals the write
> success/failure properly so that we get a correct return value.

I'm afraid that a number of hypervisors do write-discard, given the
propensity of OSes (certainly traditionally) to go poking at bits like
this without wrmsr_safe().

You either need to read the MSR back and observe that the bit has really
changed, or in this case as Thomas suggests, look at CPUID again (which
will likely be the faster option for the non-virtualised case).

~Andrew

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