linux-kernel - Re: [PATCH v2 10/14] dt-bindings: power: avs: Add support for CPR (Core Power Reduction)

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Message-ID: <5d579b36.1c69fb81.85eba.ff51@mx.google.com>
Date:   Fri, 16 Aug 2019 23:14:13 -0700
From:   Stephen Boyd <swboyd@...omium.org>
To:     Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@...aro.org>,
        Niklas Cassel <niklas.cassel@...aro.org>
Cc:     linux-arm-msm@...r.kernel.org, vireshk@...nel.org,
        bjorn.andersson@...aro.org, ulf.hansson@...aro.org,
        Rob Herring <robh@...nel.org>,
        Rob Herring <robh+dt@...nel.org>,
        Mark Rutland <mark.rutland@....com>, linux-pm@...r.kernel.org,
        devicetree@...r.kernel.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH v2 10/14] dt-bindings: power: avs: Add support for CPR (Core Power Reduction)

Quoting Niklas Cassel (2019-07-25 03:41:38)
> +       cpr@...8000 {
> +               compatible = "qcom,qcs404-cpr", "qcom,cpr";
> +               reg = <0x0b018000 0x1000>;
> +               interrupts = <0 15 IRQ_TYPE_EDGE_RISING>;
> +               clocks = <&xo_board>;
> +               clock-names = "ref";
> +               vdd-apc-supply = <&pms405_s3>;
> +               #power-domain-cells = <0>;
> +               operating-points-v2 = <&cpr_opp_table>;
> +               acc-syscon = <&tcsr>;
> +
> +               nvmem-cells = <&cpr_efuse_quot_offset1>,
> +                       <&cpr_efuse_quot_offset2>,
> +                       <&cpr_efuse_quot_offset3>,
> +                       <&cpr_efuse_init_voltage1>,
> +                       <&cpr_efuse_init_voltage2>,
> +                       <&cpr_efuse_init_voltage3>,
> +                       <&cpr_efuse_quot1>,
> +                       <&cpr_efuse_quot2>,
> +                       <&cpr_efuse_quot3>,
> +                       <&cpr_efuse_ring1>,
> +                       <&cpr_efuse_ring2>,
> +                       <&cpr_efuse_ring3>,
> +                       <&cpr_efuse_revision>;
> +               nvmem-cell-names = "cpr_quotient_offset1",
> +                       "cpr_quotient_offset2",
> +                       "cpr_quotient_offset3",
> +                       "cpr_init_voltage1",
> +                       "cpr_init_voltage2",
> +                       "cpr_init_voltage3",
> +                       "cpr_quotient1",
> +                       "cpr_quotient2",
> +                       "cpr_quotient3",
> +                       "cpr_ring_osc1",
> +                       "cpr_ring_osc2",
> +                       "cpr_ring_osc3",
> +                       "cpr_fuse_revision";
> +
> +               qcom,cpr-timer-delay-us = <5000>;
> +               qcom,cpr-timer-cons-up = <0>;
> +               qcom,cpr-timer-cons-down = <2>;
> +               qcom,cpr-up-threshold = <1>;
> +               qcom,cpr-down-threshold = <3>;
> +               qcom,cpr-idle-clocks = <15>;
> +               qcom,cpr-gcnt-us = <1>;
> +               qcom,vdd-apc-step-up-limit = <1>;
> +               qcom,vdd-apc-step-down-limit = <1>;

Are any of these qcom,* properties going to change for a particular SoC?
They look like SoC config data that should just go into the driver and
change based on the SoC compatible string.