linux-kernel - Re: [RESEND PATCH V3 1/8] perf/x86/intel: Set correct mask for TOPDOWN.SLOTS

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Message-ID: <20190828074802.GZ2369@hirez.programming.kicks-ass.net>
Date:   Wed, 28 Aug 2019 09:48:02 +0200
From:   Peter Zijlstra <peterz@...radead.org>
To:     kan.liang@...ux.intel.com
Cc:     acme@...nel.org, mingo@...hat.com, linux-kernel@...r.kernel.org,
        tglx@...utronix.de, jolsa@...nel.org, eranian@...gle.com,
        alexander.shishkin@...ux.intel.com, ak@...ux.intel.com
Subject: Re: [RESEND PATCH V3 1/8] perf/x86/intel: Set correct mask for
 TOPDOWN.SLOTS

On Mon, Aug 26, 2019 at 07:47:33AM -0700, kan.liang@...ux.intel.com wrote:
> From: Kan Liang <kan.liang@...ux.intel.com>
> 
> TOPDOWN.SLOTS(0x0400) is not a generic event. It is only available on
> fixed counter3.
> 
> Don't extend its mask to generic counters.
> 
> Signed-off-by: Kan Liang <kan.liang@...ux.intel.com>


> diff --git a/arch/x86/include/asm/perf_event.h b/arch/x86/include/asm/perf_event.h
> index 1392d5e6e8d6..457d35a75ad3 100644
> --- a/arch/x86/include/asm/perf_event.h
> +++ b/arch/x86/include/asm/perf_event.h
> @@ -167,6 +167,11 @@ struct x86_pmu_capability {
>  #define INTEL_PMC_IDX_FIXED_REF_CYCLES	(INTEL_PMC_IDX_FIXED + 2)
>  #define INTEL_PMC_MSK_FIXED_REF_CYCLES	(1ULL << INTEL_PMC_IDX_FIXED_REF_CYCLES)
>  
> +/* TOPDOWN.SLOTS: */
> +#define MSR_ARCH_PERFMON_FIXED_CTR3	0x30c
> +#define INTEL_PMC_IDX_FIXED_SLOTS	(INTEL_PMC_IDX_FIXED + 3)
> +#define INTEL_PMC_MSK_FIXED_SLOTS	(1ULL << INTEL_PMC_IDX_FIXED_SLOTS)
> +
>  /*
>   * We model BTS tracing as another fixed-mode PMC.
>   *


This whole second hunk does not belong in this patch, probably the next
one.